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| regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. hitachi single-chip microcomputer h8/3672 series h8/3672 hd64f3672 h8/3670 hd64f3670 hardware manual ade-602-239a rev. 2.0 03/20/02 hitachi, ltd. rev. 2.0, 03/02, page ii of xxii cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. rev. 2.0, 03/02, page iii of xxii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the products state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the systems operation is not guaranteed if they are accessed. rev. 2.0, 03/02, page iv of xxii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 11. index rev. 2.0, 03/02, page v of xxii preface the h8/3672 series are single-chip microcomputers made up of the high-speed h8/300h cpu employing hitachis original architecture as their cores, and the peripheral functions required to configure a system. the h8/300h cpu has an instruction set that is compatible with the h8/300 cpu. target users: this manual was written for users who will be using the h8/3672 series in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8/3672 series to the target users. refer to the h8/300h series programming manual for a detailed description of the instruction set. notes on reading this manual: in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripheral functions and electrical characteristics. in order to understand the details of the cpu's functions read the h8/300h series programming manual. in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 16, list of registers. example: bit order: the msb is on the left and the lsb is on the right. notes: when using an on-chip emulator (e10t) for h8/3672 program development and debugging, the following restrictions must be noted. 1. the 10, pin is reserved for the e10t, and cannot be used. 2. area h4000 to h4fff is used by the e10t, and is not available to the user. 3. area hf780 to hfb7f must on no account be accessed. 4. when the e10t is used, address breaks can be set as either available to the user or for use by the e10t. if address breaks are set as being used by the e10t, the address break control registers must not be accessed. 5. when the e10t is used, 10, is an input/output pin (open-drain in output mode). rev. 2.0, 03/02, page vi of xxii related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/ h8/3672 series manuals: manual title ade no. h8/3672 series hardware manual this manual h8/300h series programming manual ade-602-053 user's manuals for development tools: manual title ade no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual ade-702-247 h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series hitachi embedded workshop, hitachi debugging interface tutorial ade-702-231 hitachi embedded workshop user's manual ade-702-201 application notes: manual title ade no. single power supply f-ztat tm on-board programming ade-502-055 rev. 2.0, 03/02, page vii of xxii contents section 1 overview........................................................................................1 1.1 features .................................................................................................................... ...1 1.2 internal block diagram ................................................................................................2 1.3 pin arrangement ..........................................................................................................3 1.4 pin functions ............................................................................................................... 5 section 2 cpu................................................................................................7 2.1 address space and memory map .................................................................................8 2.2 register configuration .................................................................................................9 2.2.1 general registers.............................................................................................10 2.2.2 program counter (pc) .....................................................................................11 2.2.3 condition-code register (ccr) .......................................................................11 2.3 data formats................................................................................................................ 13 2.3.1 general register data formats.........................................................................13 2.3.2 memory data formats .....................................................................................15 2.4 instruction set............................................................................................................. .16 2.4.1 table of instructions classified by function.....................................................16 2.4.2 basic instruction formats ................................................................................25 2.5 addressing modes and effective address calculation ..................................................27 2.5.1 addressing modes ...........................................................................................27 2.5.2 effective address calculation..........................................................................29 2.6 basic bus cycle ...........................................................................................................32 2.6.1 access to on-chip memory (ram, rom) ......................................................32 2.6.2 on-chip peripheral modules ............................................................................33 2.7 cpu states.................................................................................................................. .34 2.8 usage notes................................................................................................................. 35 2.8.1 notes on data access to empty areas..............................................................35 2.8.2 eepmov instruction .......................................................................................35 2.8.3 bit manipulation instruction ............................................................................35 section 3 exception handling ........................................................................41 3.1 exception sources and vector address .........................................................................42 3.2 register descriptions ...................................................................................................43 3.2.1 interrupt edge select register 1 (iegr1).........................................................43 3.2.2 interrupt edge select register 2 (iegr2).........................................................44 3.2.3 interrupt enable register 1 (ienr1) ................................................................45 3.2.4 interrupt flag register 1 (irr1).......................................................................46 3.2.5 wakeup interrupt flag register (iwpr)...........................................................47 3.3 reset exception handling ............................................................................................48 rev. 2.0, 03/02, page viii of xxii 3.4 interrupt exception handling ....................................................................................... 48 3.4.1 external interrupts ........................................................................................... 48 3.4.2 internal interrupts ............................................................................................ 49 3.4.3 interrupt handling sequence............................................................................ 49 3.4.4 interrupt response time .................................................................................. 51 3.5 usage notes................................................................................................................. 53 3.5.1 interrupts after reset ....................................................................................... 53 3.5.2 notes on stack area use ................................................................................. 53 3.5.3 notes on rewriting port mode registers.......................................................... 53 section 4 address break................................................................................ 55 4.1 register descriptions ................................................................................................... 55 4.1.1 address break control register (abrkcr) .................................................... 56 4.1.2 address break status register (abrksr) ....................................................... 57 4.1.3 break address registers (barh, barl)........................................................ 57 4.1.4 break data registers (bdrh, bdrl) ............................................................. 57 4.2 operation................................................................................................................... .. 58 4.3 usage notes................................................................................................................. 59 section 5 clock pulse generators .................................................................. 61 5.1 system clock generator............................................................................................... 61 5.1.1 connecting crystal resonator .......................................................................... 62 5.1.2 connecting ceramic resonator ........................................................................ 62 5.1.3 external clock input method ........................................................................... 63 5.2 prescalers .................................................................................................................. .. 63 5.2.1 prescaler s ...................................................................................................... 63 5.3 usage notes................................................................................................................. 63 5.3.1 note on resonators.......................................................................................... 63 5.3.2 notes on board design.................................................................................... 64 section 6 power-down modes....................................................................... 65 6.1 register descriptions ................................................................................................... 66 6.1.1 system control register 1 (syscr1) .............................................................. 66 6.1.2 system control register 2 (syscr2) .............................................................. 68 6.1.3 module standby control register 1 (mstcr1) ............................................... 69 6.2 mode transitions and states of lsi.............................................................................. 70 6.2.1 sleep mode ..................................................................................................... 72 6.2.2 standby mode ................................................................................................. 72 6.2.3 subsleep mode................................................................................................ 72 6.3 operating frequency in active mode ........................................................................... 73 6.4 direct transition.......................................................................................................... 7 3 6.5 module standby function ............................................................................................ 73 rev. 2.0, 03/02, page ix of xxii section 7 rom ..............................................................................................75 7.1 block configuration.....................................................................................................75 7.2 register descriptions ...................................................................................................76 7.2.1 flash memory control register 1 (flmcr1) ..................................................77 7.2.2 flash memory control register 2 (flmcr2) ..................................................78 7.2.3 erase block register 1 (ebr1) ........................................................................78 7.2.4 flash memory enable register (fenr) ...........................................................79 7.3 on-board programming modes ....................................................................................79 7.3.1 boot mode ......................................................................................................80 7.3.2 programming/erasing in user program mode ..................................................82 7.4 flash memory programming/erasing ...........................................................................83 7.4.1 program/program-verify .................................................................................83 7.4.2 erase/erase-verify...........................................................................................85 7.4.3 interrupt handling when programming/erasing flash memory .........................86 7.5 program/erase protection .............................................................................................88 7.5.1 hardware protection ........................................................................................88 7.5.2 software protection .........................................................................................88 7.5.3 error protection ...............................................................................................88 section 8 ram ..............................................................................................89 section 9 i/o ports .........................................................................................91 9.1 port 1...................................................................................................................... .....91 9.1.1 port mode register 1 (pmr1)..........................................................................92 9.1.2 port control register 1 (pcr1)........................................................................93 9.1.3 port data register 1 (pdr1) ............................................................................93 9.1.4 port pull-up control register 1 (pucr1) ........................................................94 9.1.5 pin functions...................................................................................................94 9.2 port 2...................................................................................................................... .....96 9.2.1 port control register 2 (pcr2)........................................................................96 9.2.2 port data register 2 (pdr2) ............................................................................97 9.2.3 pin functions...................................................................................................97 9.3 port 5...................................................................................................................... .....98 9.3.1 port mode register 5 (pmr5)..........................................................................99 9.3.2 port control register 5 (pcr5)........................................................................100 9.3.3 port data register 5 (pdr5) ............................................................................100 9.3.4 port pull-up control register 5 (pucr5) ........................................................101 9.3.5 pin functions...................................................................................................101 9.4 port 7...................................................................................................................... .....103 9.4.1 port control register 7 (pcr7)........................................................................104 9.4.2 port data register 7 (pdr7) ............................................................................104 9.4.3 pin functions...................................................................................................105 9.5 port 8...................................................................................................................... .....106 rev. 2.0, 03/02, page x of xxii 9.5.1 port control register 8 (pcr8)........................................................................ 106 9.5.2 port data register 8 (pdr8)............................................................................ 107 9.5.3 pin functions .................................................................................................. 107 9.6 port b ...................................................................................................................... .... 109 9.6.1 port data register b (pdrb)........................................................................... 110 section 10 timer v ....................................................................................... 111 10.1 features................................................................................................................... .... 111 10.2 input/output pins ......................................................................................................... 112 10.3 register descriptions ................................................................................................... 113 10.3.1 timer counter v (tcntv) ............................................................................. 113 10.3.2 time constant registers a and b (tcora, tcorb) ...................................... 113 10.3.3 timer control register v0 (tcrv0) ............................................................... 114 10.3.4 timer control/status register v (tcsrv) ...................................................... 116 10.3.5 timer control register v1 (tcrv1) ............................................................... 117 10.4 operation.................................................................................................................. ... 118 10.4.1 timer v operation .......................................................................................... 118 10.5 timer v application examples .................................................................................... 121 10.5.1 pulse output with arbitrary duty cycle........................................................... 121 10.5.2 pulse output with arbitrary pulse width and delay from trgv input ............ 122 10.6 usage notes................................................................................................................ . 123 section 11 timer w....................................................................................... 125 11.1 features................................................................................................................... .... 125 11.2 input/output pins ......................................................................................................... 127 11.3 register descriptions ................................................................................................... 128 11.3.1 timer mode register w (tmrw) ................................................................... 129 11.3.2 timer control register w (tcrw) ................................................................. 129 11.3.3 timer interrupt enable register w (tierw)................................................... 131 11.3.4 timer status register w (tsrw).................................................................... 131 11.3.5 timer i/o control register 0 (tior0) ............................................................. 133 11.3.6 timer i/o control register 1 (tior1) ............................................................. 134 11.3.7 timer counter (tcnt) .................................................................................... 135 11.3.8 general registers a to d (gra to grd)......................................................... 135 11.4 operation.................................................................................................................. ... 136 11.4.1 normal operation............................................................................................ 136 11.4.2 pwm operation .............................................................................................. 140 11.5 operation timing......................................................................................................... 14 4 11.5.1 tcnt count timing ....................................................................................... 144 11.5.2 output compare output timing ...................................................................... 144 11.5.3 input capture timing ...................................................................................... 145 11.5.4 timing of counter clearing by compare match............................................... 146 11.5.5 buffer operation timing ................................................................................. 146 rev. 2.0, 03/02, page xi of xxii 11.5.6 timing of imfa to imfd flag setting at compare match ...............................147 11.5.7 timing of imfa to imfd setting at input capture ..........................................148 11.5.8 timing of status flag clearing ........................................................................148 11.6 usage notes................................................................................................................ . 149 section 12 watchdog timer...........................................................................151 12.1 features ................................................................................................................... ....151 12.2 register descriptions ...................................................................................................151 12.2.1 timer control/status register wd (tcsrwd) ...............................................152 12.2.2 timer counter wd (tcwd) ...........................................................................153 12.2.3 timer mode register wd (tmwd) ................................................................153 12.3 operation.................................................................................................................. ...154 section 13 serial communication interface3 (sci3) ......................................155 13.1 features ................................................................................................................... ....155 13.2 input/output pins .........................................................................................................157 13.3 register descriptions ...................................................................................................157 13.3.1 receive shift register (rsr)...........................................................................158 13.3.2 receive data register (rdr) ..........................................................................158 13.3.3 transmit shift register (tsr)..........................................................................158 13.3.4 transmit data register (tdr) .........................................................................158 13.3.5 serial mode register (smr)............................................................................159 13.3.6 serial control register 3 (scr3) .....................................................................160 13.3.7 serial status register (ssr).............................................................................162 13.3.8 bit rate register (brr) ..................................................................................164 13.4 operation in asynchronous mode ................................................................................169 13.4.1 clock ..............................................................................................................169 13.4.2 sci3 initialization ...........................................................................................170 13.4.3 data transmission ...........................................................................................171 13.4.4 serial data reception ......................................................................................173 13.5 operation in clocked synchronous mode .....................................................................177 13.5.1 clock ..............................................................................................................177 13.5.2 sci3 initialization ...........................................................................................177 13.5.3 serial data transmission .................................................................................178 13.5.4 serial data reception (clocked synchronous mode) ........................................180 13.5.5 simultaneous serial data transmission and reception .....................................182 13.6 multiprocessor communication function .....................................................................184 13.6.1 multiprocessor serial data transmission .........................................................186 13.6.2 multiprocessor serial data reception ..............................................................187 13.7 interrupts ................................................................................................................. ....191 13.8 usage notes................................................................................................................ . 192 13.8.1 break detection and processing .......................................................................192 13.8.2 mark state and break sending .........................................................................192 rev. 2.0, 03/02, page xii of xxii 13.8.3 receive error flags and transmit operations (clocked synchronous mode only) .................................................................. 192 13.8.4 receive data sampling timing and reception margin in asynchronous mode ........................................................................................ 193 section 14 a/d converter.............................................................................. 195 14.1 features................................................................................................................... .... 195 14.2 input/output pins ......................................................................................................... 197 14.3 register description..................................................................................................... 19 8 14.3.1 a/d data registers a to d (addra to addrd) ........................................... 198 14.3.2 a/d control/status register (adcsr) ............................................................ 199 14.3.3 a/d control register (adcr)......................................................................... 200 14.4 operation.................................................................................................................. ... 201 14.4.1 single mode.................................................................................................... 201 14.4.2 scan mode ...................................................................................................... 201 14.4.3 input sampling and a/d conversion time ....................................................... 202 14.4.4 external trigger input timing ......................................................................... 203 14.5 a/d conversion accuracy definitions ......................................................................... 204 14.6 usage notes................................................................................................................ . 205 14.6.1 permissible signal source impedance .............................................................. 205 14.6.2 influences on absolute accuracy ..................................................................... 205 section 15 power supply circuit ................................................................... 207 15.1 when using internal power supply step-down circuit ................................................ 207 15.2 when not using internal power supply step-down circuit ......................................... 208 section 16 list of registers ........................................................................... 209 16.1 register addresses (address order) ............................................................................. 210 16.2 register bits .............................................................................................................. .. 213 16.3 register states in each operating mode....................................................................... 216 section 17 electrical characteristics .............................................................. 219 17.1 absolute maximum ratings......................................................................................... 219 17.2 electrical characteristics.............................................................................................. 219 17.2.1 power supply voltage and operating ranges .................................................. 219 17.2.2 dc characteristics........................................................................................... 221 17.2.3 ac characteristics........................................................................................... 226 17.2.4 a/d converter characteristics ......................................................................... 229 17.2.5 watchdog timer.............................................................................................. 230 17.2.6 flash memory characteristics (preliminary) .................................................... 231 17.3 operation timing......................................................................................................... 23 3 17.4 output load condition ................................................................................................ 235 rev. 2.0, 03/02, page xiii of xxii appendix a instruction set ............................................................................237 a.1 instruction list............................................................................................................ . 237 a.2 operation code map ....................................................................................................252 a.3 number of execution states .........................................................................................255 a.4 combinations of instructions and addressing modes....................................................266 appendix b i/o port block diagrams ............................................................267 b.1 i/o port block.............................................................................................................. 267 b.2 port states in each operating state...............................................................................282 appendix c product code lineup..................................................................283 appendix d package dimensions ..................................................................284 main revisions and additions in this edition...................................................287 index .....................................................................................................295 rev. 2.0, 03/02, page xiv of xxii rev. 2.0, 03/02, page xv of xxii figures section 1 overview figure 1.1 internal block diagram............................................................................................ .2 figure 1.2 pin arrangement (fp-64e)........................................................................................3 figure 1.3 pin arrangement (fp-48f, fp-48b) ..........................................................................4 section 2 cpu figure 2.1 memory map ........................................................................................................ ....8 figure 2.2 cpu registers..................................................................................................... ......9 figure 2.3 usage of general registers .....................................................................................10 figure 2.4 relationship between stack pointer and stack area.................................................11 figure 2.5 general register data formats (1) ..........................................................................13 figure 2.5 general register data formats (2) ..........................................................................14 figure 2.6 memory data formats ............................................................................................15 figure 2.7 instruction formats ............................................................................................... ..26 figure 2.8 branch address specification in memory indirect mode .........................................29 figure 2.9 on-chip memory access cycle ..............................................................................32 figure 2.10 on-chip peripheral module access cycle (3-state a ccess) ...................................33 figure 2.11 cpu operation states............................................................................................3 4 figure 2.12 state transitions ................................................................................................ ...35 figure 2.13 example of timer configuration with two registers allocated to same address...................................................................................................... ..36 section 3 exception handling figure 3.1 reset sequence .................................................................................................... ...49 figure 3.2 stack status after exception handling .....................................................................50 figure 3.3 interrupt sequence ................................................................................................ ..52 figure 3.4 port mode register setting and interrupt request flag clearing procedure..............53 section 4 address break figure 4.1 block diagram of address break ............................................................................55 figure 4.2 address break interrupt operation example (1) ......................................................58 figure 4.2 address break interrupt operation example (2) ......................................................59 figure 4.3 operation when condition is not satisfied in branch instruction ..............................59 figure 4.4 operation when another interrupt is a ccepted at address break setting instruction ...........................................................................60 section 5 clock pulse generators figure 5.1 block diagram of clock pulse generators...............................................................61 figure 5.2 block diagram of system clock generator .............................................................61 figure 5.3 typical connection to crystal resonator.................................................................62 figure 5.4 equivalent circuit of crystal resonator...................................................................62 figure 5.5 typical connection to ceramic resonator ...............................................................62 rev. 2.0, 03/02, page xvi of xxii figure 5.6 example of external clock input ............................................................................63 figure 5.7 example of incorrect board design.........................................................................64 section 6 power-down modes figure 6.1 mode transition diagram .......................................................................................70 section 7 rom figure 7.1 flash memory block configuration ........................................................................76 figure 7.2 programming/erasing flowchart example in user program mode...........................82 figure 7.3 program/program-verify flowchart ........................................................................84 figure 7.4 erase/erase-verify flowchart .................................................................................87 section 9 i/o ports figure 9.1 port 1 pin configuration .........................................................................................9 1 figure 9.2 port 2 pin configuration .........................................................................................9 6 figure 9.3 port 5 pin configuration .........................................................................................9 8 figure 9.4 port 7 pin configuration ....................................................................................... 103 figure 9.5 port 8 pin configuration ....................................................................................... 106 figure 9.6 port b pin configuration....................................................................................... 109 section 10 timer v figure 10.1 block diagram of timer v.................................................................................. 112 figure 10.2 increment timing with internal clock ................................................................. 118 figure 10.3 increment timing with external clock ................................................................ 119 figure 10.4 ovf set timing ................................................................................................. 119 figure 10.5 cmfa and cmfb set timing ............................................................................ 119 figure 10.6 tmov output timing ........................................................................................ 120 figure 10.7 clear timing by compare match ........................................................................ 120 figure 10.8 clear timing by tmriv input............................................................................ 120 figure 10.9 pulse output example......................................................................................... 121 figure 10.10 example of pulse output synchronized to trgv input..................................... 122 figure 10.11 contention between tcntv write and clear.................................................... 123 figure 10.12 contention between tcora write and compare match ................................... 124 figure 10.13 internal clock switching and tcntv operation............................................... 124 section 11 timer w figure 11.1 timer w block diagram..................................................................................... 127 figure 11.2 free-running counter operation......................................................................... 136 figure 11.3 periodic counter operation ................................................................................. 137 figure 11.4 0 and 1 output example (toa = 0, tob = 1) ..................................................... 137 figure 11.5 toggle output example (toa = 0, tob = 1)...................................................... 138 figure 11.6 toggle output example (toa = 0, tob = 1)...................................................... 138 figure 11.7 input capture operating example ....................................................................... 139 figure 11.8 buffer operation example (input capture) .......................................................... 139 figure 11.9 pwm mode example (1) .................................................................................... 140 figure 11.10 pwm mode example (2) .................................................................................. 141 rev. 2.0, 03/02, page xvii of xxii figure 11.11 buffer operation example (output compare)....................................................141 figure 11.12 pwm mode example (tob, toc, and tod = 0: initial output values are set to 0) ...............................142 figure 11.13 pwm mode example (tob, toc, and tod = 1: initial output values are set to 1) ...............................143 figure 11.14 count timing for internal clock source ............................................................144 figure 11.15 count timing for external clock source ...........................................................144 figure 11.16 output compare output timing ........................................................................145 figure 11.17 input capture input signal timing ....................................................................145 figure 11.18 timing of counter clearing by compare match ................................................146 figure 11.19 buffer operation timing (compare match) .......................................................146 figure 11.20 buffer operation timing (input capture)...........................................................147 figure 11.21 timing of imfa to imfd flag setting at compare match .................................147 figure 11.22 timing of imfa to imfd flag setting at input capture ....................................148 figure 11.23 timing of status flag clearing by cpu.............................................................148 figure 11.24 contention between tcnt write and clear.......................................................149 figure 11.25 internal clock switching and tcnt operation..................................................150 section 12 watchdog timer figure 12.1 block diagram of watchdog timer .....................................................................151 figure 12.2 watchdog timer operation example...................................................................154 section 13 serial communication interface3 (sci3) figure 13.1 block diagram of sci3 .......................................................................................156 figure 13.2 data format in asynchronous communication....................................................169 figure 13.3 relationship between output clock and transfer data phase (asynchronous mode)(example with 8-bit data, parity, two stop bits) ...............169 figure 13.4 sample sci3 initialization flowchart ..................................................................170 figure 13.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit) .........................................................................171 figure 13.6 sample serial transmission flowchart (asynchronous mode) .............................172 figure 13.7 example sci3 operation in reception in asynchronous mode (8-bit data, parity, one stop bit) .........................................................................173 figure 13.8 sample serial data reception flowchart (asynchronous mode)(1) ......................175 figure 13.8 sample serial reception data flowchart (2)........................................................176 figure 13.9 data format in clocked synchronous communication ........................................177 figure 13.10 example of sci3 operation in transmission in clocked synchronous mode ......178 figure 13.11 sample serial transmission flowchart (clocked synchronous mode)................179 figure 13.12 example of sci3 r eception operation in clocked synchronous mode ...............180 figure 13.13 sample serial reception flowchart (clocked synchronous mode) .....................181 figure 13.14 sample flowchart of simultaneous serial transmit and receive oper ations (clocked synchronous mode).............................................................................183 figure 13.15 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) ..........................................185 rev. 2.0, 03/02, page xviii of xxii figure 13.16 sample multiprocessor serial transmission flowchart ...................................... 186 figure 13.17 sample multiprocessor serial reception flowchart (1) ...................................... 188 figure 13.17 sample multiprocessor serial reception flowchart (2) ...................................... 189 figure 13.18 example of sci3 operation in r eception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit).............................. 190 figure 13.19 receive d ata sampling timing in asynchronous mode..................................... 193 section 14 a/d converter figure 14.1 block diagram of a/d converter ........................................................................ 196 figure 14.2 a/d conversion timing...................................................................................... 202 figure 14.3 external trigger input timing............................................................................. 203 figure 14.4 a/d conversion accuracy definitions (1) ........................................................... 204 figure 14.5 a/d conversion accuracy definitions (2) ........................................................... 205 figure 14.6 analog input circuit example............................................................................. 206 section 15 power supply circuit figure 15.1 power supply connection when internal step-down circuit is used ................... 207 figure 15.2 power supply connection when internal step-down circuit is not used............. 208 section 17 electrical characteristics figure 17.1 system clock input timing................................................................................. 233 figure 17.2 5(6 low width timing ..................................................................................... 233 figure 17.3 input timing..................................................................................................... .. 233 figure 17.4 sck3 input clock timing .................................................................................. 234 figure 17.5 sci3 input/output timing in clocked synchronous mode................................... 234 figure 17.6 output load circuit ............................................................................................ 23 5 appendix b i/o port block diagrams figure b.1 port 1 block diagram (p17) ................................................................................. 267 figure b.2 port 1 block diagram (p14) ................................................................................. 268 figure b.3 port 1 block diagram (p16, p15, p12, p10) .......................................................... 269 figure b.4 port 1 block diagram (p11) ................................................................................. 270 figure b.5 port 2 block diagram (p22) ................................................................................. 271 figure b.6 port 2 block diagram (p21) ................................................................................. 272 figure b.7 port 2 block diagram (p20) ................................................................................. 273 figure b.8 port 5 block diagram (p57, p56).......................................................................... 274 figure b.9 port 5 block diagram (p55) ................................................................................. 275 figure b.10 port 5 block diagram (p54 to p50)..................................................................... 276 figure b.11 port 7 block diagram (p76) ............................................................................... 277 figure b.12 port 7 block diagram (p75) ............................................................................... 278 figure b.13 port 7 block diagram (p74) ............................................................................... 279 figure b.14 port 8 block diagram (p84 to p81)..................................................................... 280 figure b.15 port 8 block diagram (p80) ............................................................................... 281 figure b.16 port b block diagram (pb3 to pb0)................................................................... 282 rev. 2.0, 03/02, page xix of xxii appendix d package dimensions figure d.1 fp-64e package dimensions................................................................................284 figure d.2 fp-48f package dimensions ................................................................................285 figure d.3 fp-48b package dimensions ................................................................................286 rev. 2.0, 03/02, page xx of xxii rev. 2.0, 03/02, page xxi of xxii tables section 1 overview table 1.1 pin functions ...................................................................................................... .......5 table 2.1 operation notation................................................................................................. ..16 section 2 cpu table 2.2 data transfer instructions ........................................................................................1 7 table 2.3 arithmetic operations instructions (1) ......................................................................18 table 2.3 arithmetic operations instructions (2) ......................................................................19 table 2.4 logic operations instructions...................................................................................20 table 2.5 shift instructions................................................................................................. .....20 table 2.6 bit manipulation instructions (1)..............................................................................21 table 2.6 bit manipulation instructions (2)..............................................................................22 table 2.7 branch instructions ................................................................................................ ..23 table 2.8 system control instructions......................................................................................24 table 2.9 block data transfer instructions ..............................................................................25 table 2.10 addressing modes.................................................................................................. 27 table 2.11 absolute address access ranges............................................................................28 table 2.12 effective address calculation (1) ...........................................................................30 table 2.12 effective address calculation (2) ...........................................................................31 section 3 exception handling table 3.1 exception sources and vector address.....................................................................42 table 3.2 interrupt wait states.............................................................................................. ...51 section 4 address break table 4.1 access and data bus used .......................................................................................57 section 5 clock pulse generators table 5.1 crystal resonator parameters ...................................................................................62 section 6 power-down modes table 6.1 operating frequency and waiting time....................................................................67 table 6.2 transition mode after sleep instruction execution and interrupt handling .............71 table 6.3 internal state in each operating mode......................................................................71 section 7 rom table 7.1 setting programming modes ....................................................................................79 table 7.2 boot mode oper ation ...............................................................................................81 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible .......................................................................................................... ......82 table 7.4 reprogram data computation table.........................................................................85 table 7.5 additional-program data computation table ...........................................................85 table 7.6 programming time ..................................................................................................8 5 rev. 2.0, 03/02, page xxii of xxii section 10 timer v table 10.1 pin configuration................................................................................................. 112 table 10.2 clock signals to input to tcntv and counting conditions.................................. 115 section 11 timer w table 11.1 timer w functions........................................................................................... 126 table 11.2 pin configuration ............................................................................................. 127 section 13 serial communication interface3 (sci3) table 13.1 pin configuration ............................................................................................. 157 table 13.2 examples of brr settings for various bit rates (asynchronous mode) (1)...... 165 table 13.2 examples of brr settings for various bit rates (asynchronous mode) (2)...... 166 table 13.2 examples of brr settings for various bit rates (asynchronous mode) (3)...... 167 table 13.3 maximum bit rate for each frequency (asynchronous mode) ......................... 167 table 13.4 brr settings for various bit rates (clocked synchronous mode).................... 168 table 13.5 ssr status flags and r eceive d ata handling.................................................... 174 table 13.6 sci3 interrupt requests .................................................................................... 191 section 14 a/d converter table 14.1 pin configuration................................................................................................. 197 table 14.2 analog input channels and corresponding addr registers ................................ 198 table 14.3 a/d conversion time (single mode) ................................................................... 203 section 17 electrical characteristics table 17.1 absolute maximum ratings ................................................................................. 219 table 17.2 dc characteristics (1) .......................................................................................... 22 1 table 17.2 dc characteristics (2) .......................................................................................... 22 5 table 17.3 ac characteristics ............................................................................................... 2 26 table 17.4 serial interface (sci3) timing ............................................................................. 228 table 17.5 a/d converter characteristics .............................................................................. 229 table 17.6 watchdog timer characteristics........................................................................... 230 table 17.7 flash memory characteristics (preliminary) ......................................................... 231 appendix a instruction set table a.1 instruction set.................................................................................................... ... 239 table a.2 operation code map (1)........................................................................................ 252 table a.2 operation code map (2)........................................................................................ 253 table a.2 operation code map (3)........................................................................................ 254 table a.3 number of cycles in each instruction.................................................................... 256 table a.4 number of cycles in each instruction.................................................................... 257 table a.5 combinations of instructions and addressing modes ............................................. 266 rev. 2.0, 03/02, page 1 of 298 section 1 overview 1.1 features high-speed h8/300h central processing unit with an internal 16-bit architecture ? upward-compatible with h8/300 cpu on an object level ? sixteen 16-bit general registers ? 62 basic instructions various peripheral functions ? timer v (8-bit timer) ? timer w (16-bit timer) ? watchdog timer ? sci3 (asynchronous or clocked synchronous serial communication interface) ? 10-bit a/d converter on-chip memory product classification model rom ram flash memory version h8/3672 hd64f3672 16 kbytes 2,048 bytes (f-ztat tm version) h8/3670 hd64f3670 8 kbytes 2,048 bytes general i/o ports ? i/o pins: 26 i/o pins, including 5 large current ports (i ol = 20 ma, @v ol = 1.5 v) ? input-only pins: 4 input pins (also used for analog input) supports various power-down modes compact package package code body size pin pitch lqfp-64 fp-64e 10.0 10.0 mm 0.5 mm lqfp-48 fp-48f 10.0 10.0 mm 0.65 mm lqfp-48 fp-48b 7.0 7.0 mm 0.5 mm note: f-ztat tm is a trademark of hitachi, ltd. rev. 2.0, 03/02, page 2 of 298 1.2 internal block diagram p17/ /trgv p16 p15 p14/ p12 p11 p10 p57 p56 p55/ / p54/ p53/ p52/ p51/ p50/ pb3/an3 pb2/an2 pb1/an1 pb0/an0 v cl v ss v cc test av cc p22/txd p21/rxd p20/sck3 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci p76/tmov p75/tmciv p74/tmriv e10t_0 e10t_1 e10t_2 osc1 osc2 port 1 data bus (upper) cpu h8/300h rom ram data bus (lower) timer w sci3 watchdog timer timer v a/d converter port b cmos large current port i ol = 20 ma @ v ol = 1.5 v system clock generator port 2 port 5 address bus port 7 port 8 figure 1.1 internal block diagram rev. 2.0, 03/02, page 3 of 298 1.3 pin arrangement nc nc av cc nc nc v cl test v ss osc2 osc1 v cc p50/ p51/ nc nc 1 2 3 4 5 6 7 8 9 10111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc p22/txd p21/rxd p20/sck3 e10t_2 e10t_1 e10t_0 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc p14/ p15 p16 p17/ /trgv nc nc nc nc pb3/an3 pb2/an2 pb1/an1 pb0/an0 nc nc nc nc p76/tmov p75/tmciv p74/tmriv p57 p56 p12 p11 p10 p55/ / p54/ p53/ p52/ nc nc h8/3672 top view note: do not connect nc pins (these pins are not connected to the internal circuitry). figure 1.2 pin arrangement (fp-64e) rev. 2.0, 03/02, page 4 of 298 avcc nc nc v cl test vss osc2 osc1 vcc p50/ p51/ 123456789101112 36 35 34 33 32 31 30 29 28 27 26 25 p22/txd p21/rxd p20/sck3 e10t_2 e10t_1 e10t_0 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 p14/ p15 p16 p17/ /trgv nc nc nc nc pb3/an3 pb2/an2 pb1/an1 pb0/an0 p76/tmov p75/tmciv p74/tmriv p57 p56 p12 p11 p10 p55/ / p54/ p53/ p52/ h8/3672 top view note: do not connect nc pins (these pins are not connected to the internal circuitry). figure 1.3 pin arrangement (fp-48f, fp-48b) rev. 2.0, 03/02, page 5 of 298 1.4 pin functions table 1.1 pin functions pin no. type symbol fp-64e fp-48f, fp-48b i/o functions power source pins v cc 12 10 input power supply pin. connect this pin to the system power supply. v ss 9 7 input ground pin. connect this pin to the system power supply (0v). av cc 31input analog power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. v cl 64input internal step-down power supply pin. connect a capacitor of around 0.1 m f between this pin and the vss pin for stabilization. clock pins osc1 11 9 input osc2 10 8 output these pins connect to a crystal or ceramic resonator for system clocks, or can be used to input an external clock. see section 5, clock pulse generators, for a typical connection. system control 5(6 7 5 input reset pin. when this driven low, the chip is reset. test 8 6 input test pin. connect this pin to vss. interrupt pins 10, 35 25 input non-maskable interrupt request input pin. ,54 , ,54 51, 54 37, 40 input external interrupt request input pins. can select the rising or falling edge. :.3 to :.3 13, 14, 19 to 22 11 to 16 input external interrupt request input pins. can select the rising or falling edge. rev. 2.0, 03/02, page 6 of 298 pin no. type symbol fp-64e fp-48f, fp-48b i/o functions timer v tmov 30 24 output this is an output pin for waveforms generated by the output compare function. tmciv 29 23 input external event input pin. tmriv 28 22 input counter reset input pin. trgv 54 40 input counter start trigger input pin. timer w ftci 36 26 input external event input pin. ftioa to ftiod 37 to 40 27 to 30 i/o output compare output/ input capture input/ pwm output pin serial com- munication txd 46 36 output transmit data output pin interface (sci) rxd 45 35 input receive data input pin sck3 44 34 i/o clock i/o pin a/d converter an3 to an0 59 to 62 45 to 48 input analog input pin $'75* 22 16 input a/d converter trigger input pin. i/o ports pb3 to pb0 59 to 62 45 to 48 input 4-bit input port. p17 to p14, p12 to p10 54 to 51, 25 to 23 40 to 37, 19 to 17 i/o 7-bit i/o port. p22 to p20 46 to 44 36 to 34 i/o 3-bit i/o port. p57 to p50 27, 26, 22 to 19, 14, 13 21, 20, 16 to 11 i/o 8-bit i/o port p76 to p74 30 to 28 24 to 22 i/o 3-bit i/o port p84 to p80 40 to 36 30 to 26 i/o 5-bit i/o port. e10t e10t_0, e10t_1, e10t_2 41, 42, 43 31, 32, 33 interface pin for e10t emulator rev. 2.0, 03/02, page 7 of 298 section 2 cpu this lsi has an h8/300h cpu with an internal 32-bit architecture that is upward-compatible with the h8/300cpu, and supports only normal mode, which has a 64-kbyte address space. upward-compatible with h8/300 cpus ? can execute h8/300 cpus object programs ? additional eight 16-bit extended registers ? 32-bit transfer and arithmetic and logic instructions are added ? signed multiply and divide instructions are added. general-register architecture ? sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers sixty-two basic instructions ? 8/16/32-bit data transfer and arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:24,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @Cern] ? absolute address [@aa:8, @aa:16, @aa:24] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] 64-kbyte address space high-speed operation ? all frequently-used instructions execute in one or two states ? 8/16/32-bit register-register add/subtract : 2 state ? 8 8-bit register-register multiply : 14 states ? 16 8-bit register-register divide : 14 states ? 16 16-bit register-register multiply : 22 states ? 32 16-bit register-register divide : 22 states power-down state ? transition to power-down state by sleep instruction cpu30h2b_000020020300 rev. 2.0, 03/02, page 8 of 298 2.1 address space and memory map the address space of this lsi is 64 kbytes, which includes the program area and the data area. figure 2.1 shows the memory map. interrupt vector on-chip rom (16 kbytes) e10t control program area (4 kbytes) not used (1-kbyte work area for flash memory programming&e10t) internal i/o register h'0000 h'0033 h'0034 h'3fff h'4000 h'4fff e10t control program area (4 kbytes) h'4000 h'4fff h'f780 h'fb7f h'ff7f h'ff80 h'fb80 h'f780 h'fb7f h'fb80 h'ffff hd64f3672 (flash memory version) hd64f3670 (flash memory version) interrupt vector on-chip rom (8 kbytes) not used not used h'0000 h'0033 h'0034 h'ff7f h'ff80 h'ffff h'1fff (1-kbyte user area) on-chip ram (2 kbytes) (1-kbyte work area for flash memory programming&e10t) internal i/o register (1-kbyte user area) on-chip ram (2 kbytes) figure 2.1 memory map rev. 2.0, 03/02, page 9 of 298 2.2 register configuration the h8/300h cpu has the internal registers shown in figure 2.2. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), and an 8-bit condition code register (ccr). pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp pc ccr i ui :stack pointer :program counter :condition-code register :interrupt mask bit :user bit :half-carry flag :user bit :negative flag :zero flag :overflow flag :carry flag er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 h u n z v c general registers (ern) control registers (cr) legend figure 2.2 cpu registers rev. 2.0, 03/02, page 10 of 298 2.2.1 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. figure 2.3 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. the usage of each register can be selected independently. general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.4 shows the stack. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.3 usage of general registers rev. 2.0, 03/02, page 11 of 298 sp (er7) free area stack area figure 2.4 relationship between stack pointer and stack area 2.2.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). the pc is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. some instructions leave flag bits unchanged. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a.1, instruction list. rev. 2.0, 03/02, page 12 of 298 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception- handling sequence. 6 ui undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. rev. 2.0, 03/02, page 13 of 298 2.3 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.3.1 general register data formats figure 2.5 shows the data formats in general registers. 70 70 msb lsb msb lsb 70 43 don't care don't care don't care 70 43 70 don't care 65432 710 70 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type general register data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.5 general register data formats (1) rev. 2.0, 03/02, page 14 of 298 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb ern en rn rnh rnl msb lsb : general register er : general register e : general register r : general register rh : general register rl : most significant bit : least significant bit data type data format general register word data word data rn en longword data legend ern figure 2.5 general register data formats (2) rev. 2.0, 03/02, page 15 of 298 2.3.2 memory data formats figure 2.6 shows the data formats in memory. the h8/300h cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. this also applies to instruction fetches. when er7 (sp) is used as an address register to access the stack, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.6 memory data formats rev. 2.0, 03/02, page 16 of 298 2.4 instruction set 2.4.1 table of instructions classified by function the h8/300h cpu has 62 instructions. tables 2.2 to 2.9 summarize the instructions in each functional category. the notation used in tables 2.2 to 2.9 is defined below. table 2.1 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication division logical and logical or ? logical xor ? move ? not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers/address registers (er0 to er7). rev. 2.0, 03/02, page 17 of 298 table 2.2 data transfer instructions instruction size * function mov b/w/l (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) ? rd, cannot be used in this lsi. movtpe b rs ? (eas) cannot be used in this lsi. pop w/l @sp+ ? rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn ? @Csp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @Csp. push.l ern is identical to mov.l ern, @Csp. note: * refers to the operand size. b: byte w: word l: longword rev. 2.0, 03/02, page 18 of 298 table 2.3 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs ? rd, rd #imm ? rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx brd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 ? rd, rd 2 ? rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 ? rd, rd 2 ? rd, rd 4 ? rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust ? rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs ? rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. mulxs b/w rd rs ? rd performs signed multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. divxu b/w rd rs ? rd performs unsigned division on data in two general registers: either 16 bits 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits 16 bits ? 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword rev. 2.0, 03/02, page 19 of 298 table 2.3 arithmetic operations instructions (2) instruction size * function divxs b/w rd rs ? rd performs signed division on data in two general registers: either 16 bits 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits 16 bits ? 16-bit quotient and 16-bit remainder. cmp b/w/l rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 C rd ? rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. note: * refers to the operand size. b: byte w: word l: longword rev. 2.0, 03/02, page 20 of 298 table 2.4 logic operations instructions instruction size * function and b/w/l rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) ? (rd) takes the one's complement of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.5 shift instructions instruction size * function shal shar b/w/l rd (shift) ? rd performs an arithmetic shift on general register contents. shll shlr b/w/l rd (shift) ? rd performs a logical shift on general register contents. rotl rotr b/w/l rd (rotate) ? rd rotates general register contents. rotxl rotxr b/w/l rd (rotate) ? rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte w: word l: longword rev. 2.0, 03/02, page 21 of 298 table 2.6 bit manipulation instructions (1) instruction size * function bset b 1 ? ( rev. 2.0, 03/02, page 22 of 298 table 2.6 bit manipulation instructions (2) instruction size * function bxor bixor b b c ? ( rev. 2.0, 03/02, page 23 of 298 table 2.7 branch instructions instruction size function bcc * branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address. jsr branches to a subroutine at a specified address. rts returns from a subroutine note: * bcc is the general name for conditional branch instructions. rev. 2.0, 03/02, page 24 of 298 table 2.8 system control instructions instruction size * function trapa starts trap-instruction exception handling. rte returns from an exception-handling routine. sleep causes a transition to a power-down state. ldc b/w (eas) ? ccr moves the source operand contents to the ccr. the ccr size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr ? (ead), exr ? (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ? ccr, exr #imm ? exr logically ands the ccr with immediate data. orc b ccr #imm ? ccr, exr #imm ? exr logically ors the ccr with immediate data. xorc b ccr ? #imm ? ccr, exr ? #imm ? exr logically xors the ccr with immediate data. nop pc + 2 ? pc only increments the program counter. note: * refers to the operand size. b: byte w: word rev. 2.0, 03/02, page 25 of 298 table 2.9 block data transfer instructions instruction size function eepmov.b if r4l 1 0 then repeat @er5+ ? @er6+, r4lC1 ? r4l until r4l = 0 else next; eepmov.w if r4 1 0 then repeat @er5+ ? @er6+, r4C1 ? r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction begins as soon as the transfer is completed. 2.4.2 basic instruction formats h8/300h cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). figure 2.7 shows examples of instruction formats. rev. 2.0, 03/02, page 26 of 298 operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. register field specifies a general register. address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. a24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (h'00). condition field specifies the branching condition of bcc instructions. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm rn rm op ea(disp) op cc ea(disp) bra d:8 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.7 instruction formats rev. 2.0, 03/02, page 27 of 298 2.5 addressing modes and effective address calculation 2.5.1 addressing modes the following describes the h8/300h cpu. in this lsi, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. the h8/300h cpu supports the eight addressing modes listed in table 2.10. each instruction uses a subset of these addressing modes. addressing modes that can be used differ depending on the instruction. for details, refer to appendix a.4, combinations of instructions and addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.10 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:24,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @Cern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 register directrn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. register indirect@ern the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand on memory. rev. 2.0, 03/02, page 28 of 298 register indirect with displacement@(d:16, ern) or @(d:24, ern) a 16-bit or 24-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. a 16-bit displacement is sign-extended when added. register indirect with post-increment or pre-decrement@ern+ or @-ern register indirect with post-increment@ern+ the register field of the instruction code specifies an address register (ern) the lower 24 bits of which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for the word or longword access, the register value should be even. register indirect with pre-decrement@-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for the word or longword access, the register value should be even. absolute address@aa:8, @aa:16, @aa:24 the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 8 bits are a sign extension. a 24-bit absolute address can access the entire address space. the access ranges of absolute addresses for the series of this lsi are those shown in table 2.11, because the upper 8 bits are ignored. table 2.11 absolute address access ranges absolute address access range 8 bits (@aa:8) h'ff00 to h'ffff 16 bits (@aa:16) h'0000 to h'ffff 24 bits (@aa:24) h'0000 to h'ffff immediate#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. rev. 2.0, 03/02, page 29 of 298 the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. program-counter relative@(d:8, pc) or @(d:16, pc) this mode is used in the bsr instruction. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is C126 to +128 bytes (C63 to +64 words) or C32766 to +32768 bytes (C16383 to +16384 words) from the branch instruction. the resulting value should be an even number. memory indirect@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byte of the memory operand is ignored, generating a 24-bit branch address. figure 2.8 shows how to specify branch address for in memory indirect mode. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff). note that the first part of the address range is also the exception vector area. specified by @aa:8 branch address dummy figure 2.8 branch address specification in memory indirect mode 2.5.2 effective address calculation table 2.12 indicates how effective addresses are calculated in each addressing mode. in this lsi the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. rev. 2.0, 03/02, page 30 of 298 table 2.12 effective address calculation (1) no 1 r op 31 0 23 2 3 register indirect with displacement @(d:16,ern) or @(d:24,ern) 4 r op disp r op rm op rn 31 0 0 r op 23 0 31 0 disp 31 0 31 0 23 0 23 0 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement ?register indirect with post-increment @ern+ ?register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand is general register contents. the value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size. rev. 2.0, 03/02, page 31 of 298 table 2.12 effective address calculation (2) no 5 op 23 0 abs @aa:8 7 h'ffff op 23 0 @aa:16 @aa:24 abs 15 16 23 0 op abs 6 op imm #xx:8/#xx:16/#xx:32 8 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 7 program-counter relative @(d:8,pc) @(d:16,pc) memory indirect @@aa:8 23 0 disp 0 23 0 disp op 23 op 8 abs 23 0 abs h'0000 7 8 0 15 23 0 15 h'00 16 legend r, rm,rn : op : disp : imm : abs : register field operation field displacement immediate data absolute address pc contents sign extension memory contents rev. 2.0, 03/02, page 32 of 298 2.6 basic bus cycle cpu operation is synchronized by a system clock (?) or a subclock (? sub ). the period from a rising edge of ? or ? sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.9 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub ? or ? figure 2.9 on-chip memory access cycle rev. 2.0, 03/02, page 33 of 298 2.6.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits or 16 bits depending on the register. for description on the data bus width and number of accessing states of each register, refer to section 16.1, register addresses. registers with 16-bit data bus width can be accessed by word size only. registers with 8-bit data bus width can be accessed by byte or word size. when a register with 8-bit data bus width is accessed by word size, access is completed in two cycles. in two-state access, the operation timing is the same as that for on-chip memory. figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub ? or ? figure 2.10 on-chip peripheral module access cycle (3-state access) rev. 2.0, 03/02, page 34 of 298 2.7 cpu states there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active mode. in the program halt state there are a sleep mode, and standby mode. these states are shown in figure 2.11. figure 2.12 shows the state transitions. for details on program execution state and program halt state, refer to section 6, power-down modes. for details on exception processing, refer to section 3, exception handling. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode sleep mode power-down modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized standby mode figure 2.11 cpu operation states rev. 2.0, 03/02, page 35 of 298 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs interrupt source exception- handling complete reset occurs figure 2.12 state transitions 2.8 usage notes 2.8.1 notes on data access to empty areas the address space of this lsi includes empty areas in addition to the rom, ram, and on-chip i/o registers areas available to the user. when data is transferred from cpu to empty areas, the transferred data will be lost. this action may also cause the cpu to malfunction. when data is transferred from an empty area to cpu, the contents of the data cannot be guaranteed. 2.8.2 eepmov instruction eepmov is a block-transfer instruction and transfers the byte size of data indicated by r4l, which starts from the address indicated by r5, to the address indicated by r6. set r4l and r6 so that the end address of the destination address (value of r6 + r4l) does not exceed h'ffff (the value of r6 must not change from h'ffff to h'0000 during execution). 2.8.3 bit manipulation instruction the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. special care is required when using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. bit manipulation for two registers assigned to the same address example: bit manipulation for the timer load register and timer counter (applicable for timer b and timer c, not for the series of this lsi.) rev. 2.0, 03/02, page 36 of 298 figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. data is read in byte units. 2. the cpu sets or resets the bit to be manipulated with the bit manipulation instruction. 3. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal bus figure 2.13 example of timer configuration with two registers allocated to same address example 2: the bset instruction is executed for port 5. p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins and output low-level signals. an example to output a high-level signal at p50 with a bset instruction is shown below. rev. 2.0, 03/02, page 37 of 298 prior to executing bset p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 00111111 pdr5 10000000 bset instruction executed bset #0, @pdr5 the bset instruction is executed for port 5. after executing bset p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 00111111 pdr5 0 1 00000 1 description on operation when the bset instruction is executed, first the cpu reads port 5. since p57 and p56 are input pins, the cpu reads the pin states (low-level and high-level input). p55 to p50 are output pins, so the cpu reads the value in pdr5. in this example pdr5 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr5 data to h'41. finally, the cpu writes h'41 to pdr5, completing execution of bset. as a result of the bset instruction, bit 0 in pdr5 becomes 1, and p50 outputs a high-level signal. however, bits 7 and 6 of pdr5 end up with different values. to prevent this problem, store a copy of the pdr5 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr5. rev. 2.0, 03/02, page 38 of 298 prior to executing bset mov.b #80, r0l mov.b r0l, @ram0 mov.b r0l, @pdr5 the pdr5 value (h'80) is written to a work area in memory (ram0) as well as to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 00111111 pdr5 10000000 ram0 10000000 bset instruction executed bset #0, @ram0 the bset instruction is executed designating the pdr5 work area (ram0). after executing bset mov.b @ram0, r0l mov.b r0l, @pdr5 the work area (ram0) value is written to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 00111111 pdr5 1000000 1 ram0 1000000 1 bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 5 control register pcr5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins that output low-level signals. an example of setting the p50 pin as an input pin by the bclr instruction is shown below. it is assumed that a high-level signal will be input to this input pin. rev. 2.0, 03/02, page 39 of 298 prior to executing bclr p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 00111111 pdr5 10000000 bclr instruction executed bclr #0, @pcr5 the bclr instruction is executed for pcr5. after executing bclr p57 p56 p55 p54 p53 p52 p51 p50 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level pcr5 1 111111 0 pdr5 10000000 description on operation when the bclr instruction is executed, first the cpu reads pcr5. since pcr5 is a write-only register, the cpu reads a value of h'ff, even though the pcr5 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, h'fe is written to pcr5 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr5 becomes 0, making p50 an input port. however, bits 7 and 6 in pcr5 change to 1, so that p57 and p56 change from input pins to output pins. to prevent this problem, store a copy of the pcr5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to pcr5. rev. 2.0, 03/02, page 40 of 298 prior to executing bclr mov.b #3f, r0l mov.b r0l, @ram0 mov.b r0l, @pcr5 the pcr5 value (h'3f) is written to a work area in memory (ram0) as well as to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 00111111 pdr5 10000000 ram0 00111111 bclr instruction executed bclr #0, @ram0 the bclr instructions executed for the pcr5 work area (ram0). after executing bclr mov.b @ram0, r0l mov.b r0l, @pcr5 the work area (ram0) value is written to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0011111 0 pdr5 10000000 ram0 0011111 0 rev. 2.0, 03/02, page 41 of 298 section 3 exception handling exception handling may be caused by a reset, a trap instruction (trapa), or interrupts. reset a reset has the highest exception priority. exception handling starts as soon as the reset is cleared by the 5(6 pin. the chip is also reset when the watchdog timer overflows, and exception handling starts. exception handling is the same as exception handling by the 5(6 pin. trap instruction exception handling starts when a trap instruction (trapa) is executed. the trapa instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. exception handling can be executed at all times in the program execution state. interrupts external interrupts other than nmi and internal interrupts other than address break are masked by the i bit in ccr, and kept masked while the i bit is set to 1. exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. rev. 2.0, 03/02, page 42 of 298 3.1 exception sources and vector address table 3.1 shows the vector addresses and priority of each exception handling. when more than one interrupt is requested, handling is performed from the interrupt with the highest priority. table 3.1 exception sources and vector address relative module exception sources vector number vector address priority 5(6 pin watchdog timer reset 0 h'0000 to h'0001 high ? reserved for system use 1 to 6 h'0002 to h'000d external interrupt pin nmi 7 h'000e to h'000f trap instruction (#0) 8 h'0010 to h'0011 (#1) 9 h'0012 to h'0013 (#2) 10 h'0014 to h'0015 cpu (#3) 11 h'0016 to h'0017 address break break conditions satisfied 12 h'0018 to h'0019 cpu direct transition by executing the sleep instruction 13 h'001a to h'001b irq0 14 h'001c to h'001d irq3 17 h'0022 to h'0023 external interrupt pin wkp 18 h'0024 to h'0025 ? reserved for system use 20 h'0028 to h'0029 timer w input capture a/compare match a input capture b/compare match b input capture c/compare match c input capture d/compare match d timer w overflow 21 h'002a to h'002b timer v timer v compare match a timer v compare match b timer v overflow 22 h'002c to h'002d sci3 sci3 receive data full sci3 transmit data empty sci3 transmit end sci3 receive error 23 h'002e to h'002f a/d converter a/d conversion end 25 h'0032 to h'0033 low rev. 2.0, 03/02, page 43 of 298 3.2 register descriptions interrupts are controlled by the following registers. interrupt edge select register 1 (iegr1) interrupt edge select register 2 (iegr2) interrupt enable register 1 (ienr1) interrupt flag register 1 (irr1) wakeup interrupt flag register (iwpr) 3.2.1 interrupt edge select register 1 (iegr1) iegr1 selects the direction of an edge that generates interrupt requests of pins and ,54 and ,54 . bit bit name initial value r/w description 7 ? 0 - reserved this bit is always read as 0. 6 5 4 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 3 ieg3 0 r/w irq3 edge select 0: falling edge of ,54 pin input is detected 1: rising edge of ,54 pin input is detected 2 1 ? ? 0 0 ? ? reserved these bits are always read as 0. 0 ieg0 0 r/w irq0 edge select 0: falling edge of ,54 pin input is detected 1: rising edge of ,54 pin input is detected rev. 2.0, 03/02, page 44 of 298 3.2.2 interrupt edge select register 2 (iegr2) iegr2 selects the direction of an edge that generates interrupt requests of the pins $'75* and :.3 to :.3 . bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1. 5 wpeg5 0 r/w wkp5 edge select 0: falling edge of :.3 ( $'75* ) pin input is detected 1: rising edge of :.3 ( $'75* ) pin input is detected 4 wpeg4 0 r/w wkp4 edge select 0: falling edge of :.3 pin input is detected 1: rising edge of :.3 pin input is detected 3 wpeg3 0 r/w wkp3 edge select 0: falling edge of :.3 pin input is detected 1: rising edge of :.3 pin input is detected 2 wpeg2 0 r/w wkp2 edge select 0: falling edge of :.3 pin input is detected 1: rising edge of :.3 pin input is detected 1 wpeg1 0 r/w wkp1edge select 0: falling edge of :.3 pin input is detected 1: rising edge of :.3 pin input is detected 0 wpeg0 0 r/w wkp0 edge select 0: falling edge of :.3 pin input is detected 1: rising edge of :.3 pin input is detected rev. 2.0, 03/02, page 45 of 298 3.2.3 interrupt enable register 1 (ienr1) ienr1 enables direct transition interrupts, and external pin interrupts. bit bit name initial value r/w description 7 iendt 0 r/w direct transfer interrupt enable when this bit is set to 1, direct transition interrupt requests are enabled. 6 ? 0 ? reserved this bit is always read as 0. 5 ienwp 0 r/w wakeup interrupt enable this bit is an enable bit, which is common to the pins :.3 to :.3 . when the bit is set to 1, interrupt requests are enabled. 4 ? 1 ? reserved this bit is always read as 1. 3 ien3 0 r/w irq3 interrupt enable when this bit is set to 1, interrupt requests of the ,54 pin are enabled. 2 1 ? ? 0 0 ? ? reserved these bits are always read as 0. 0 ien0 0 r/w irq0 interrupt enable when this bit is set to 1, interrupt requests of the ,54 pin are enabled. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed. rev. 2.0, 03/02, page 46 of 298 3.2.4 interrupt flag register 1 (irr1) irr1 is a status flag register for direct transition interrupts, and ,54 and ,54 interrupt requests. bit bit name initial value r/w description 7 irrdt 0 r/w direct transfer interrupt request flag [setting condition] when a direct transfer is made by executing a sleep instruction while dton in syscr2 is set to 1. [clearing condition] when irrdt is cleared by writing 0 6 ? 0 ? reserved this bit is always read as 0. 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1. 3 irri3 0 r/w irq3 interrupt request flag [setting condition] when ,54 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri3 is cleared by writing 0 2 1 ? ? 0 0 ? ? reserved these bits are always read as 0. 0 irrl0 0 r/w irq0 interrupt request flag [setting condition] when ,54 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri0 is cleared by writing 0 rev. 2.0, 03/02, page 47 of 298 3.2.5 wakeup interrupt flag register (iwpr) iwpr is a status flag register for :.3 to :.3 interrupt requests. bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1. 5 iwpf5 0 r/w wkp5 interrupt request flag [setting condition] when :.3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf5 is cleared by writing 0. 4 iwpf4 0 r/w wkp4 interrupt request flag [setting condition] when :.3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf4 is cleared by writing 0. 3 iwpf3 0 r/w wkp3 interrupt request flag [setting condition] when :.3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf3 is cleared by writing 0. 2 iwpf2 0 r/w wkp2 interrupt request flag [setting condition] when :.3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf2 is cleared by writing 0. 1 iwpf1 0 r/w wkp1 interrupt request flag [setting condition] when :.3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf1 is cleared by writing 0. 0 iwpf0 0 r/w wkp0 interrupt request flag [setting condition] when :.3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf0 is cleared by writing 0. rev. 2.0, 03/02, page 48 of 298 3.3 reset exception handling when the 5(6 pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-up, hold the 5(6 pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the 5(6 pin low for at least 10 system clock cycles. when the 5(6 pin goes high after being held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. the reset exception handling sequence is as follows : 1. set the i bit in the condition code register (ccr) to 1. 2. the cpu generates a reset exception handling vector address (from h'0000 to h'0001), the data in that address is sent to the program counter (pc) as the start address, and program execution starts from that address. 3.4 interrupt exception handling 3.4.1 external interrupts there are external interrupts, nmi, irq3, irq0, and wkp. nmi nmi interrupt is requested by input falling edge to pin 10, . nmi is the highest interrupt, and can always be accepted without depending on the i bit value in ccr. irq3 to irq0 interrupts irq3 to irq0 interrupts are requested by input signals to pins ,54 to ,54 . these four interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg3 to ieg0 in iegr1. when pins ,54 to ,54 are designated for interrupt input in pmr1 and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. when irq3 to irq0 interrupt is accepted, the i bit is set to 1 in ccr. these interrupts can be masked by setting bits ien3 to ien0 in ienr1. wkp5 to wkp0 interrupts wkp5 to wkp0 interrupts are requested by input signals to pins :.3 5 to :.3 0. these six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits wpeg5 to wpeg0 in iegr2. rev. 2.0, 03/02, page 49 of 298 when pins :.3 to :.3 are designated for interrupt input in pmr5 and the designated signal edge is input, the corresponding bit in iwpr is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bit ienwp in ienr1. vector fetch ? internal address bus internal read signal internal write signal internal data bus (16 bits) internal processing initial program instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) initial program instruction (2) (3) (2) (1) reset cleared figure 3.1 reset sequence 3.4.2 internal interrupts each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. for direct transfer interrupt requests generated by execution of a sleep instruction, this function is included in irr1 and ienr1. when an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the cpu of an interrupt. when this interrupt is accepted, the i bit is set to 1 in ccr. these interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 interrupt handling sequence interrupts are controlled by an interrupt controller. interrupt operation is described as follows. rev. 2.0, 03/02, page 50 of 298 1. if an interrupt occurs while the nmi or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. when multiple interrupt requests are generated, the interrupt controller requests to the cpu for the interrupt handling with the highest priority at that time according to table 3.1. other interrupt requests are held pending. 3. the cpu accepts the nmi or address break without depending on the i bit value. other interrupt requests are accepted, if the i bit is cleared to 0 in ccr; if the i bit is set to 1, the interrupt request is held pending. 4. if the cpu accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. first, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.2. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. then, the i bit of ccr is set to 1, masking further interrupts excluding the nmi and address break. upon return from interrupt handling, the values of i bit and other bits in ccr will be restored and returned to the values prior to the start of interrupt exception handling. 6. next, the cpu generates the vector address corresponding to the accepted interrupt, and transfers the address to pc as a start address of the interrupt handling-routine. then a program starts executing from the address indicated in pc. figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram. pc and ccr saved to stack sp (r7) sp C 1 sp C 2 sp C 3 sp C 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling legend: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr * 3 pch pcl 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word length, starting from an even-numbered address. 3. ignored when returning from the interrupt handling routine. figure 3.2 stack status after exception handling rev. 2.0, 03/02, page 51 of 298 3.4.4 interrupt response time table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.2 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 13 15 to 27 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction. rev. 2.0, 03/02, page 52 of 298 vector fetch ? internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp C 2 (6) sp C 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.3 interrupt sequence rev. 2.0, 03/02, page 53 of 298 3.5 usage notes 3.5.1 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.w #xx: 16, sp). 3.5.2 notes on stack area use when word data is accessed, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @Csp) or pop rn (mov.w @sp+, rn) to save or restore register values. 3.5.3 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, ,54 to ,54 , and :.3 to :.3 , the interrupt request flag may be set to 1. figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ? ccr i bit 0 ? figure 3.4 port mode register setting and interrupt request flag clearing procedure rev. 2.0, 03/02, page 54 of 298 rev. 2.0, 03/02, page 55 of 298 section 4 address break the address break simplifies on-board program debugging. it requests an address break interrupt when the set break condition is satisfied. the interrupt request is not affected by the i bit of ccr. break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. with the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. figure 4.1 shows a block diagram of the address break. barh barl bdrh bdrl abrkcr abrksr internal address bus comparator interrupt generation control circuit internal data bus comparator interrupt legend: barh, barl: break address register bdrh, bdrl: break data register abrkcr: address break control register abrksr: address break status register figure 4.1 block diagram of address break 4.1 register descriptions address break has the following registers. address break control register (abrkcr) address break status register (abrksr) break address register (barh, barl) break data register (bdrh, bdrl) abk0001a_000020020300 rev. 2.0, 03/02, page 56 of 298 4.1.1 address break control register (abrkcr) abrkcr sets address break conditions. bit bit name initial value r/w description 7 rtinte 1 r/w rte interrupt enable when this bit is 0, the interrupt immediately after executing rte is masked and then one instruction must be executed. when this bit is 1, the interrupt is not masked. 6 5 csel1 csel0 0 0 r/w r/w condition select 1 and 0 these bits set address break conditions. 00: instruction execution cycle 01: cpu data read cycle 10: cpu data write cycle 11: cpu data read/write cycle 4 3 2 acmp2 acmp1 acmp0 0 0 0 r/w r/w r/w address compare condition select 2 to 0 these bits comparison condition between the address set in bar and the internal address bus. 000: compares 16-bit addresses 001: compares upper 12-bit addresses 010: compares upper 8-bit addresses 011: compares upper 4-bit addresses 1xx: reserved (setting prohibited) 1 0 dcmp1 dcmp0 0 0 r/w r/w data compare condition select 1 and 0 these bits set the comparison condition between the data set in bdr and the internal data bus. 00: no data comparison 01: compares lower 8-bit data between bdrl and data bus 10: compares upper 8-bit data between bdrh and data bus 11: compares 16-bit data between bdr and data bus legend: x: don't care. when an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. table 4.1 shows the access and data bus used. when an i/o register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. for details on data widths of each register, see section 16.1, register addresses. rev. 2.0, 03/02, page 57 of 298 table 4.1 access and data bus used word access byte access even address odd address even address odd address rom space upper 8 bits lower 8 bits upper 8 bits upper 8 bits ram space upper 8 bits lower 8 bits upper 8 bits upper 8 bits i/o register with 8-bit data bus width upper 8 bits upper 8 bits upper 8 bits upper 8 bits i/o register with 16-bit data bus width upper 8 bits lower 8 bits 4.1.2 address break status register (abrksr) abrksr consists of the address break interrupt flag and the address break interrupt enable bit. bit bit name initial value r/w description 7 abif 0 r/w address break interrupt flag [setting condition] when the condition set in abrkcr is satisfied [clearing condition] when 0 is written after abif=1 is read 6 abie 0 r/w address break interrupt enable when this bit is 1, an address break interrupt request is enabled. 5 to 0 all 1 reserved these bits are always read as 1. 4.1.3 break address registers (barh, barl) barh and barl are 16-bit read/write registers that set the address for generating an address break interrupt. when setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. the initial value of this register is h'ffff. 4.1.4 break data registers (bdrh, bdrl) bdrh and bdrl are 16-bit read/write registers that set the data for generating an address break interrupt. bdrh is compared with the upper 8-bit data bus. bdrl is compared with the lower 8- bit data bus. when memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. therefore, comparison data must be set in bdrh for byte access. for word access, the data bus used depends on the address. see section rev. 2.0, 03/02, page 58 of 298 4.1.1, address break control register (abrkcr), for details. the initial value of this register is undefined. 4.2 operation when the abif and abie bits in abrksr are set to 1, the address break function generates an interrupt request to the cpu. the abif bit in abrksr is set to 1 by the combination of the address set in bar, the data set in bdr, and the conditions set in abrkcr. when the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. the address break interrupt is not masked because of the i bit in ccr of the cpu. figures 4.2 show the operation examples of the address break interrupt setting. nop instruc- tion prefetch register setting ? abrkcr = h'80 ? bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 0258 address bus f interrupt request 025a 025c 025e sp-2 sp-4 nop instruc- tion prefetch mov instruc- tion 1 prefetch mov instruc- tion 2 prefetch internal processing stack save interrupt acceptance underline indicates the address to be stacked. when the address break is specified in instruction execution cycle figure 4.2 address break interrupt operation example (1) rev. 2.0, 03/02, page 59 of 298 mov instruc- tion 1 prefetch register setting ? abrkcr = h'a0 ? bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 025c address bus f interrupt request 025e 0260 025a 0262 0264 sp-2 mov instruc- tion 2 prefetch nop instruc- tion prefetch mov instruc- tion execution next instru- ction prefetch internal processing stack save nop instruc- tion prefetch interrupt acceptance underline indicates the address to be stacked. when the address break is specified in the data read cycle figure 4.2 address break interrupt operation example (2) 4.3 usage notes when an address break is set to an instruction after a conditional branch instruction, and the instruction set when the condition of the branch instruction is not satisfied is executed (see figure 4.3), note that an address break interrupt request is not generated. therefore an address break must not be set to the instruction after a conditional branch instruction. 0134 adress bus adress break interrupt request 0136 102a 0138 [register setting] bne instruction prefetch nop instruction prefetch mov instruction prefetch nop instruction prefetch abrkcr=h'80 bar=h'0136 012a mov.b . . . : : 0134 bne * 0136 nop 0138 nop : : [program] figure 4.3 operation when condition is not satisfied in branch instruction rev. 2.0, 03/02, page 60 of 298 when another interrupt request is accepted before an instruction to which an address break is set is executed, exception handling of an address break interrupt is not executed. however, the abif bit is set to 1 (see figure 4.4). therefore the abif bit must be read during exception handling of an address break interrupt. 0142 0144 0146 * mov.b #h'23,r1h mov.b #h'45,r1h mov.b #h'67,r1h 0142 0144 0146 sp-2 sp-4 001c 0900 abif [register setting] external interrupt underlined indicates the addoress to be stacked. abrkcr=h'80 bar=h'0144 001c 0900 : : [program] mov instruction prefetch mov instruction prefetch mov instruction prefetch stack save vector fetch internal processing external interrupt acceptance internal processing adress bus external interrupt acceptance adress break interrupt request figure 4.4 operation when another interrupt is accepted at address break setting instruction rev. 2.0, 03/02, page 61 of 298 section 5 clock pulse generators clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including a system clock pulse generator. the system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. figure 5.1 shows a block diagram of the clock pulse generators. system clock oscillator duty correction circuit system clock divider prescaler s (13 bits) osc 1 osc 2 system clock pulse generator ? osc (f osc ) ? osc (f osc ) ?/2 to ?/8192 ? ? osc /8 ? osc ? osc /16 ? osc /32 ? osc /64 figure 5.1 block diagram of clock pulse generators the basic clock signals that drive the cpu and on-chip peripheral modules are ?. the system clock is divided into ?/8192 to ?/2 by prescaler s and they are supplied to respective peripheral modules. 5.1 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. figure 5.2 shows a block diagram of the system clock generator. lpm lpm: low-power mode (standby mode, subsleep mode) 2 1 osc osc figure 5.2 block diagram of system clock generator cpg0300a_000020020300 rev. 2.0, 03/02, page 62 of 298 5.1.1 connecting crystal resonator figure 5.3 shows a typical method of connecting a crystal resonator. an at-cut parallel-resonance crystal resonator should be used. figure 5.4 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 5.1 should be used. 1 2 c 1 c 2 osc osc c = c = 12 pf 20% 12 figure 5.3 typical connection to crystal resonator c s c 0 r s osc 1 osc 2 l s figure 5.4 equivalent circuit of crystal resonator table 5.1 crystal resonator parameters frequency (mhz) 2481016 r s (max) 500 w 120 w 80 w 60 w 50 w c 0 (max) 7 pf 7 pf 7 pf 7 pf 7 pf 5.1.2 connecting ceramic resonator figure 5.5 shows a typical method of connecting a ceramic resonator. osc 1 osc 2 c 1 c 2 c 1 = 30 pf 10% c 2 = 30 pf 10% figure 5.5 typical connection to ceramic resonator rev. 2.0, 03/02, page 63 of 298 5.1.3 external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 5.6 shows a typical connection. the duty cycle of the external clock signal must be 45 to 55%. osc 1 external clock input osc 2 open figure 5.6 example of external clock input 5.2 prescalers 5.2.1 prescaler s prescaler s is a 13-bit counter using the system clock (?) as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by the on-chip peripheral modules. the divider ratio can be set separately for each on-chip peripheral function. in active mode and sleep mode, the clock input to prescaler s is determined by the division factor designated by ma2 to ma0 in syscr2. 5.3 usage notes 5.3.1 note on resonators resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator element manufacturer. design the circuit so that the resonator element never receives voltages exceeding its maximum rating. rev. 2.0, 03/02, page 64 of 298 5.3.2 notes on board design when using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the osc 1 and osc 2 pins. other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.7). osc 1 osc 2 c 1 c 2 signal a signal b avoid figure 5.7 example of incorrect board design rev. 2.0, 03/02, page 65 of 298 section 6 power-down modes this lsi has five modes of operation after a reset. these include a normal active mode and three power-down modes, in which power consumption is significantly reduced. module standby mode reduces power consumption by selectively halting on-chip module functions. active mode the cpu and all on-chip peripheral modules are operable on the system clock. the system clock frequency can be selected from ?osc, ?osc/8, ?osc/16, ?osc/32, and ?osc/64. sleep mode the cpu halts. on-chip peripheral modules are operable on the system clock. standby mode the cpu and all on-chip peripheral modules halt. subsleep mode the cpu and all on-chip peripheral modules halt. i/o ports keep the same states as before the transition. module standby mode independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. lpw3003a_000020020300 rev. 2.0, 03/02, page 66 of 298 6.1 register descriptions the registers related to power-down modes are listed below. system control register 1 (syscr1) system control register 2 (syscr2) module standby control register 1 (mstcr1) 6.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit selects the mode to transit after the execution of the sleep instruction. 0: a transition is made to sleep mode 1: a transition is made to standby mode. for details, see table 6.2. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, to active mode or sleep mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. the relationship between the specified value and the number of wait states is shown in table 6.1. when an external clock is to be used, the minimum value (sts2 = sts1 = sts0 =1) is recommended. 3 to 0 ? 0 ? reserved these bits are always read as 0. rev. 2.0, 03/02, page 67 of 298 table 6.1 operating frequency and waiting time sts2 sts1 sts0 waiting time 16 mhz 10 mhz 8 mhz 4 mhz 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 1.0 1.6 2.0 4.1 8.2 16.4 32.8 1 0 32,768 states 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 4.1 6.6 8.2 16.4 32.8 65.5 131.1 100 131,072 states 8.2 13.1 16.4 32.8 65.5 131.1 262.1 1 1,024 states 0.06 0.10 0.13 0.26 0.51 1.02 2.05 10 128 states 0.00 0.01 0.02 0.03 0.06 0.13 0.26 1 16 states 0.00 0.00 0.00 0.00 0.01 0.02 0.03 note: time unit is ms rev. 2.0, 03/02, page 68 of 298 6.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7 smsel 0 r/w sleep mode selection this bit selects the mode to transit after the execution of a sleep instruction, as well as bit ssby of syscr1. for details, see table 6.2. 6 ? 0 ? reserved this bit is always read as 0. 5 dton 0 r/w direct transfer on flag this bit selects the mode to transit after the execution of a sleep instruction, as well as bit ssby of syscr1. for details, see table 6.2. 4 3 2 ma2 ma1 ma0 0 0 0 r/w r/w r/w active mode clock select 2 to 0 these bits select the operating clock frequency in active and sleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 0xx: f osc 100: f osc /8 101: f osc /16 110: f osc /32 111: f osc /64 1 0 ? ? 0 0 ? ? reserved these bits are always read as 0. legend x: don't care. rev. 2.0, 03/02, page 69 of 298 6.1.3 module standby control register 1 (mstcr1) mstcr1 allows the on-chip peripheral modules to enter a standby state in module units. bit bit name initial value r/w description 7 6 ? ? 0 ? ? reserved these bits are always read as 0. 5 msts3 0 r/w sci3 module standby sci3 enters standby mode when this bit is set to 1 4 mstad 0 r/w a/d converter module standby a/d converter enters standby mode when this bit is set to 1 3 mstwd 0 r/w watchdog timer module standby watchdog timer enters standby mode when this bit is set to 1.when the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 msttw 0 r/w timer w module standby timer w enters standby mode when this bit is set to 1 1 msttv 0 r/w timer v module standby timer v enters standby mode when this bit is set to 1 0 ? 0 ? reserved this bit is always read as 0. rev. 2.0, 03/02, page 70 of 298 6.2 mode transitions and states of lsi figure 6.1 shows the possible transitions among these operating modes. a transition is made from the program execution state to the program halt state of the program by executing a sleep instruction. interrupts allow for returning from the program halt state to the program execution state of the program. a direct transition from active mode to active mode changes the operating frequency. 5(6 input enables transitions from a mode to the reset state. table 6.2 shows the transition conditions of each mode after the sleep instruction is executed and a mode to return by an interrupt. table 6.3 shows the internal states of the lsi in each mode. reset state standby mode active mode sleep mode subsleep mode program halt state program execution state program halt state sleep instruction sleep instruction interrupt direct transition interrupt notes: 1. to make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. details on the mode transition conditions are given in table 6.2. interrupt sleep instruction interrupt figure 6.1 mode transition diagram rev. 2.0, 03/02, page 71 of 298 table 6.2 transition mode after sleep instruction execution and interrupt handling dton ssby smsel transition mode after sleep instruction execution transition mode due to interrupt 000sl eep mode active mode 0 1 subsleep mode active mode 1 x standby mode active mode 1x0 * active mode (direct transition) legend: x: dont care. * when a state transition is performed while smsel is 1, timer v, sci3, and the a/d converter are reset, and all registers are set to their initial values. to use these functions after entering active mode, reset the registers. table 6.3 internal state in each operating mode function active mode sleep mode subsleep mode standby mode system clock oscillator functioning functioning halted halted instructions functioning halted halted halted cpu operations registers functioning retained retained retained ram functioning retained retained retained io ports functioning retained retained register contents are retained, but output is the high-impedance state. irq3, irq0 functioning functioning functioning functioning external interrupts wkp5 to wkp0 functioning functioning functioning functioning timer v functioning functioning reset reset peripheral functions timer w functioning functioning retained retained (if internal clock f is selected as a count clock, the counter is incremented by a subclock) watchdog timer functioning functioning retained retained (functioning if the internal oscillator is selected as a count clock) sci3 functioning functioning reset reset a/d converter functioning functioning reset reset rev. 2.0, 03/02, page 72 of 298 6.2.1 sleep mode in sleep mode, cpu operation is halted but the on-chip peripheral modules function at the clock frequency set by the ma2 to ma0 bits in syscr2. cpu register contents are retained. when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the requested interrupt is disabled in the interrupt enable register. a transition is made to subactive mode when the bit is 1. when the 5(6 pin goes low, the cpu goes into the reset state and sleep mode is cleared. 6.2.2 standby mode in standby mode, the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. however, as long as the rated voltage is supplied, the contents of cpu registers, on- chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be retained as long as the voltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an interrupt. when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2Csts0 in syscr1 has elapsed, and interrupt exception handling starts. standby mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the 5(6 pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the 5(6 pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the 5(6 pin is driven high. 6.2.3 subs leep mode in subsleep mode, the system clock oscillator is halted, and operation of the cpu and on-chip peripheral modules is halted. as long as a required voltage is applied, the contents of cpu registers, the on-chip ram, and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an interrupt. when an interrupt is requested, the system clock oscillator starts to oscillate. subsleep mode is cleared and an interrupt exception handling starts when the time set in bits sts2 to sts0 in syscr1 elapses. subsleep mode is not cleared if the i bit of ccr is 1 or the interrupt is disabled in the interrupt enable bit. rev. 2.0, 03/02, page 73 of 298 6.3 operating frequency in active mode operation in active mode is clocked at the frequency designated by the ma2 to ma0 bits in syscr2. the operating frequency changes to the set frequency after sleep instruction execution. 6.4 direct transition the cpu can execute programs in active mode. the operating frequency can be changed by making a transition directly from active mode to active mode. a direct transition can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. the direct transition also enables operating frequency modification in active mode. after the mode transition, direct transition interrupt exception handling starts. if the direct transition interrupt is disabled in interrupt enable register 1, a transition is made instead to sleep mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. 6.5 module standby function the module-standby function can be set to any peripheral module. in module standby mode, the clock supply to modules stops to enter the power-down mode. module standby mode enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds to each module in mstcr1 and mstcr2 to 1 and cancels the mode by clearing the bit to 0. rev. 2.0, 03/02, page 74 of 298 rev. 2.0, 03/02, page 75 of 298 section 7 rom the features of the 20-kbyte (4 kbytes of them are the e10t control program area) flash memory built into hd64f3672 are summarized below. programming/erase methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: 1 kbyte 4 blocks, 16 kbytes 1 block. to erase the entire flash memory, each block must be erased in turn. reprogramming capability ? the flash memory can be reprogrammed up to 1,000 times. on-board programming ? on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. automatic bit rate adjustment ? for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. programming/erasing protection ? sets software protection against flash memory programming/erasing. 7.1 block configuration figure 7.1 shows the block configuration of 20-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 1 kbyte 4 blocks and 16 kbytes 1 block. erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. rom3160a_000020020300 rev. 2.0, 03/02, page 76 of 298 h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0481 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'08ff h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'4fff h'4f80 h'4f81 h'4f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1kbyte erase unit 1kbyte erase unit 1kbyte erase unit 1kbyte erase unit 16 kbytes erase unit figure 7.1 flash memory block configuration 7.2 register descriptions the flash memory has the following registers. flash memory control register 1 (flmcr1) flash memory control register 2 (flmcr2) erase block register 1 (ebr1) flash memory enable register (fenr) rev. 2.0, 03/02, page 77 of 298 7.2.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 7.4, flash memory programming/erasing. bit bit name initial value r/w description 7 0 reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit to 1 in flmcr1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1. 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase- verify mode is cancelled. 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program-verify mode is cancelled. 1e 0 r/werase when this bit is set to 1, and while the swe=1 and esu=1 bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1, and while the swe=1 and psu=1 bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. rev. 2.0, 03/02, page 78 of 298 7.2.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see 7.5.3, error protection, for details. 6 to 0 all 0 reserved these bits are always read as 0. 7.2.3 erase block register 1 (ebr1) ebr1 specifies the flash memory erase area block. ebr1 is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 to 5 all 0 reserved these bits are always read as 0. 4 eb4 0 r/w when this bit is set to 1, 16 kbytes of h'1000 to h'4fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'0000 to h'03ff will be erased. rev. 2.0, 03/02, page 79 of 298 7.2.4 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memory control registers, flmcr1, flmcr2, and ebr1. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 all 0 reserved these bits are always read as 0. 7.3 on-board programming modes there is a mode for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the test pin settings, 10, pin settings, and input level of each port, as shown in table 7.1. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 7.1 setting programming modes test 10, 10, e10t_0 pb0 pb1 pb2 lsi state after reset end 0 1 xxxxuser mode 0 0 1 x x x boot mode legend : x: dont care. rev. 2.0, 03/02, page 80 of 298 7.3.1 boot mode table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 7.4, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 7.3. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'f780 to h'feef is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci3 (by clearing the re and te bits in scr3 to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high (pcr22 = 1, p22 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the test pin and 10, pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and nmi pin input levels in boot mode. rev. 2.0, 03/02, page 81 of 298 table 7.2 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host when data h'55 is received. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation ? measures low-level period of receive data h'00. ? calculates bit rate and sets brr in sci3. ? transmits data h'00 to host as adjustment end indication. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase rev. 2.0, 03/02, page 82 of 298 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency range of lsi 19,200 bps 16 mhz 9,600 bps 8 to 16 mhz 4,800 bps 4 to 16 mhz 2,400 bps 2 to 16 mhz 7.3.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 7.2 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 7.4, flash memory programming/erasing. ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 7.2 programming/erasing flowchart example in user program mode rev. 2.0, 03/02, page 83 of 298 7.4 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4.1, program/program-verify and section 7.4.2, erase/erase-verify, respectively. 7.4.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 7.6 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words or in longwords from the address to which a dummy write was performed. 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. rev. 2.0, 03/02, page 84 of 298 start end of programming note: * the rts instruction must not be used during the following 1. and 2. periods. 1. a period between 128-byte data programming to flash memory and the p bit clearing 2. a period between dummy writing of h'ff to a verify address and verify data reading set swe bit in flmcr1 write pulse application subroutine wait 1 m s apply write pulse * end sub set psu bit in flmcr1 wdt enable disable wdt wait 50 m s set p bit in flmcr1 wait (wait time=programming time) clear p bit in flmcr1 wait 5 m s clear psu bit in flmcr1 wait 5 m s n= 1 m= 0 no no no yes yes yes yes wait 4 m s wait 2 m s wait 2 m s apply write pulse set pv bit in flmcr1 set block start address as verify address h'ff dummy write to verify address read verify data verify data = write data? reprogram data computation additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 m= 0 ? increment address programming failure no clear swe bit in flmcr1 wait 100 m s no yes n 6? no yes n 6 ? wait 100 m s n 1000 ? n ? n + 1 write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area apply write pulse sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory * figure 7.3 program/program-verify flowchart rev. 2.0, 03/02, page 85 of 298 table 7.4 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 101 1 1 1 remains in erased state table 7.5 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 7.6 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 note: time shown in m s. 7.4.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr1). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in longwords from the address to which a dummy write was performed. rev. 2.0, 03/02, page 86 of 298 6. if the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 interrupt handling when programming/erasing flash memory all interrupts, including the 10, interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. rev. 2.0, 03/02, page 87 of 298 erase start set ebr1 enable wdt wait 1 m s wait 100 m s swe bit ? 1 n ? 1 esu bit ? 1 e bit ? 1 wait 10 m s e bit ? 0 wait 10 m s esu bit ? 10 10 m s disable wdt read verify data increment address verify data + all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address wait 20 m s wait 2 m s ev bit ? 1 wait 100 m s end of erasing note: * the rts instruction must not be used during a period between dummy writing of h'ff to a verify address and verify data reading. swe bit ? 0 wait 4 m s ev bit ? 0 n 100 ? wait 100 m s erase failure swe bit ? 0 wait 4 m s ev bit ? 0 n ? n + 1 ye s no ye s ye s ye s ye s no no no * figure 7.4 erase/erase-verify flowchart rev. 2.0, 03/02, page 88 of 298 7.5 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) are initialized. in a reset via the 5(6 pin, the reset state is not entered unless the 5(6 pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the 5(6 pin low for the 5(6 pulse width specified in the ac characteristics section. 7.5.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h'00, erase protection is set for all blocks. 7.5.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) immediately after exception handling excluding a reset during programming/erasing when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re- entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset. rev. 2.0, 03/02, page 89 of 298 section 8 ram this lsi has 2 kbytes of on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling two-state access by the cpu to both byte data and word data. ram0400a_000020020300 rev. 2.0, 03/02, page 90 of 298 rev. 2.0, 03/02, page 91 of 298 section 9 i/o ports the series of this lsi has twenty-six general i/o ports and four general input-only ports. port 8 is a large current port, which can drive 20 ma (@v ol = 1.5 v) when a low level signal is output. any of these ports can become an input port immediately after a reset. they can also be used as i/o pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. the registers for selecting these functions can be divided into two types: those included in i/o ports and those included in each on-chip peripheral module. general i/o ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. for functions in each port, see appendix b.1, i/o port block diagrams. for the execution of bit manipulation instructions to the port control register and port data register, see section 2.8.3, bit manipulation instruction. 9.1 port 1 port 1 is a general i/o port also functioning as irq interrupt input pins and a timer v input pin. figure 9.1 shows its pin configuration. p17/ /trgv p16 p15 p14/ p12 p11 p10 port 1 figure 9.1 port 1 pin configuration port 1 has the following registers. port mode register 1 (pmr1) port control register 1 (pcr1) port data register 1 (pdr1) port pull-up control register 1 (pucr1) rev. 2.0, 03/02, page 92 of 298 9.1.1 port mode register 1 (pmr1) pmr1 switches the functions of pins in port 1 and port 2. bit bit name initial value r/w description 7 irq3 0 r/w p17/ ,54 /trgv pin function switch this bit selects whether pin p17/ ,54 /trgv is used as p17 or as ,54 /trgv. 0: general i/o port 1: ,54 /trgv input pin 6 5 ? ? 0 0 ? ? reserved these bits are always read as 0. 4 irq0 0 r/w p14/ ,54 pin function switch this bit selects whether pin p14/ ,54 is used as p14 or as ,54 . 0: general i/o port 1: ,54 input pin 3 ? 1 ? reserved this bit is always read as 1. 2 ? 0r/wreserved this bit must always be cleared to 0 (setting to 1 is disabled). 1 txd 0 r/w p22/txd pin function switch this bit selects whether pin p22/txd is used as p22 or as txd. 0: general i/o port 1: txd output pin 0 ? 0 ? reserved these bits are always read as 0. rev. 2.0, 03/02, page 93 of 298 9.1.2 port control register 1 (pcr1) pcr1 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 0 0 0 0 ? 0 0 0 w w w w ? w w w when the corresponding pin is designated in pmr1 as a general i/o pin, setting a pcr1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bit 3 is a reserved bit. 9.1.3 port data register 1 (pdr1) pdr1 is a general i/o port data register of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 ? p12 p11 p10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w pdr1 stores output data for port 1 pins. if pdr1 is read while pcr1 bits are set to 1, the value stored in pdr1 are read. if pdr1 is read while pcr1 bits are cleared to 0, the pin states are read regardless of the value stored in pdr1. bit 3 is a reserved bit. this bit is always read as 1. rev. 2.0, 03/02, page 94 of 298 9.1.4 port pull-up control register 1 (pucr1) pucr1 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w only bits for which pcr1 is cleared are valid. the pull-up mos of p17 to p14 and p12 to p10 pins enter the on- state when these bits are set to 1, while they enter the off- state when these bits are cleared to 0. bit 3 is a reserved bit. this bit is always read as 1. 9.1.5 pin functions the correspondence between the register specification and the port functions is shown below. p17/ ,54 ,54 /trgv pin register pmr1 pcr1 bit name irq3 pcr17 pin function setting value 0 0 p17 input pin 1 p17 output pin 1x ,54 input/trgv input pin legend x: don't care. p16 pin register pcr1 bit name pcr16 pin function setting value 0 p16 input pin 1 p16 output pin rev. 2.0, 03/02, page 95 of 298 p15 pin register pcr1 bit name pcr15 pin function setting value 0 p15 input pin 1 p15 output pin p14/ ,54 ,54 pin register pmr1 pcr1 bit name irq0 pcr14 pin function setting value 0 0 p14 input pin 1 p14 output pin 1x ,54 input pin legend x: don't care. p12 pin register pcr1 bit name pcr12 pin function 0 p12 input pin setting value 1 p12 output pin p11 pin register pcr1 bit name pcr11 pin function 0 p11 input pin setting value 1 p11 output pin p10 pin register pcr1 bit name pcr10 pin function setting value 0 p10 input pin 1 p10 output pin rev. 2.0, 03/02, page 96 of 298 9.2 port 2 port 2 is a general i/o port also functioning as a sci3 i/o pin. each pin of the port 2 is shown in figure 9.2. the register settings of pmr1 and sci3 have priority for functions of the pins for both uses. p22/txd p21/rxd p20/sck3 port 2 figure 9.2 port 2 pin configuration port 2 has the following registers. port control register 2 (pcr2) port data register 2 (pdr2) 9.2.1 port control register 2 (pcr2) pcr2 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 2. bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reserved 2 1 0 pcr22 pcr21 pcr20 0 0 0 w w w when each of the port 2 pins p22 to p20 functions as an general i/o port, setting a pcr2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. rev. 2.0, 03/02, page 97 of 298 9.2.2 port data register 2 (pdr2) pdr2 is a general i/o port data register of port 2. bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? 1 1 1 1 1 ? ? ? ? ? reserved these bits are always read as 1. 2 1 0 p22 p21 p20 0 0 0 r/w r/w r/w pdr2 stores output data for port 2 pins. if pdr2 is read while pcr2 bits are set to 1, the value stored in pdr2 is read. if pdr2 is read while pcr2 bits are cleared to 0, the pin states are read regardless of the value stored in pdr2. 9.2.3 pin functions the correspondence between the register specification and the port functions is shown below. p22/txd pin register pmr1 pcr2 bit name txd pcr22 pin function setting value 0 0 p22 input pin 1 p22 output pin 1 x txd output pin legend x: don't care. p21/rxd pin register scr3 pcr2 bit name re pcr21 pin function setting value 0 0 p21 input pin 1 p21 output pin 1 x rxd input pin legend x: don't care. rev. 2.0, 03/02, page 98 of 298 p20/sck3 pin register scr3 smr pcr2 bit name cke1 cke0 com pcr20 pin function setting value 0 0 0 0 p20 input pin 1 p20 output pin 0 0 1 x sck3 output pin 0 1 x x sck3 output pin 1 x x x sck3 input pin legend x: don't care. 9.3 port 5 port 5 is a general i/o port also functioning as an a/d trigger input pin and wakeup interrupt input pin. each pin of the port 5 is shown in figure 9.3. p57 p56 p55/ / p54/ p53/ p52/ p51/ p50/ port 5 figure 9.3 port 5 pin configuration port 5 has the following registers. port mode register 5 (pmr5) port control register 5 (pcr5) port data register 5 (pdr5) port pull-up control register 5 (pucr5) rev. 2.0, 03/02, page 99 of 298 9.3.1 port mode register 5 (pmr5) pmr5 switches the functions of pins in port 5. bit bit name initial value r/w description 7 pof7 0 r/w p57 pin function switch 0: general i/o port 1: nmos open-drain output 6 pof6 0 r/w p56 pin function switch 0: general i/o port 1: nmos open-drain output 5 wkp5 0 r/w p55/ :.3 / $'75* pin function switch selects whether pin p55/ :.3 / $'75* is used as p55 or as :.3 / $'75* input. 0: general i/o port 1: :.3 / $'75* input pin 4 wkp4 0 r/w p54/ :.3 pin function switch selects whether pin p54/ :.3 is used as p54 or as :.3 . 0: general i/o port 1: :.3 input pin 3 wkp3 0 r/w p53/ :.3 pin function switch selects whether pin p53/ :.3 is used as p53 or as :.3 . 0: general i/o port 1: :.3 input pin 2 wkp2 0 r/w p52/ :.3 pin function switch selects whether pin p52/ :.3 is used as p52 or as :.3 . 0: general i/o port 1: :.3 input pin 1 wkp1 0 r/w p51/ :.3 pin function switch selects whether pin p51/ :.3 is used as p51 or as :.3 . 0: general i/o port 1: :.3 input pin 0 wkp0 0 r/w p50/ :.3 pin function switch selects whether pin p50/ :.3 is used as p50 or as :.3 . 0: general i/o port 1: :.3 input pin rev. 2.0, 03/02, page 100 of 298 9.3.2 port control register 5 (pcr5) pcr5 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 5 pins p57 to p50 functions as an general i/o port, setting a pcr5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.3.3 port data register 5 (pdr5) pdr5 is a general i/o port data register of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w stores output data for port 5 pins. if pdr5 is read while pcr5 bits are set to 1, the value stored in pdr5 are read. if pdr5 is read while pcr5 bits are cleared to 0, the pin states are read regardless of the value stored in pdr5. rev. 2.0, 03/02, page 101 of 298 9.3.4 port pull-up control register 5 (pucr5) pucr5 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved these bits are always read as 0. 5 4 3 2 1 0 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w only bits for which pcr5 is cleared are valid. the pull-up mos of the corresponding pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 9.3.5 pin functions the correspondence between the register specification and the port functions is shown below. p57 pin register pmr5 pcr5 bit name pof7 pcr57 pin function setting value x 0 p57 input pin 0 1 cmos output 1 1 nmos open-drain output legend x: don't care. p56 pin register pmr5 pcr5 bit name pof6 pcr56 pin function setting value x 0 p56 input pin 0 1 cmos output 1 1 nmos open-drain output legend x: don't care. rev. 2.0, 03/02, page 102 of 298 p55/ :.3 :.3 / $'75 $'75* * pin register pmr5 pcr5 bit name wkp5 pcr55 pin function setting value 0 0 p55 input pin 1 p55 output pin 1x :.3 / $'75* input pin legend x: don't care. p54/ :.3 :.3 pin register pmr5 pcr5 bit name wkp4 pcr54 pin function setting value 0 0 p54 input pin 1 p54 output pin 1x :.3 input pin legend x: don't care. p53/ :.3 :.3 pin register pmr5 pcr5 bit name wkp3 pcr53 pin function setting value 0 0 p53 input pin 1 p53 output pin 1x :.3 input pin legend x: don't care. p52/ :.3 :.3 pin register pmr5 pcr5 bit name wkp2 pcr52 pin function setting value 0 0 p52 input pin 1 p52 output pin 1x :.3 input pin legend x: don't care. rev. 2.0, 03/02, page 103 of 298 p51/ :.3 :.3 pin register pmr5 pcr5 bit name wkp1 pcr51 pin function setting value 0 0 p51 input pin 1 p51 output pin 1x :.3 input pin legend x: don't care. p50/ :.3 :.3 pin register pmr5 pcr5 bit name wkp0 pcr50 pin function setting value 0 0 p50 input pin 1 p50 output pin 1x :.3 input pin legend x: don't care. 9.4 port 7 port 7 is a general i/o port also functioning as a timer v i/o pin. each pin of the port 7 is shown in figure 9.4. the register setting of tcsrv in timer v has priority for functions of pin p76/tmov. the pins, p75/tmciv and p74/tmriv, are also functioning as timer v input ports that are connected to the timer v regardless of the register setting of port 7. p76/tmov p75/tmciv p74/tmriv port 7 figure 9.4 port 7 pin configuration port 7 has the following registers. port control register 7 (pcr7) port data register 7 (pdr7) rev. 2.0, 03/02, page 104 of 298 9.4.1 port control register 7 (pcr7) pcr7 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 7. bit bit name initial value r/w description 7 ?? ? reserved 6 5 4 pcr76 pcr75 pcr74 0 0 0 w w w setting a pcr7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. note that the tcsrv setting of the timer v has priority for deciding input/output direction of the p76/tmov pin. 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? ? reserved 9.4.2 port data register 7 (pdr7) pdr7 is a general i/o port data register of port 7. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 p76 p75 p74 0 0 0 r/w r/w r/w pdr7 stores output data for port 7 pins. if pdr7 is read while pcr7 bits are set to 1, the value stored in pdr7 is read. if pdr7 is read while pcr7 bits are cleared to 0, the pin states are read regardless of the value stored in pdr7. 3 2 1 0 ? ? ? ? 1 1 1 1 ? ? ? ? reserved these bits are always read as 1. rev. 2.0, 03/02, page 105 of 298 9.4.3 pin functions the correspondence between the register specification and the port functions is shown below. p76/tmov pin register tcsrv pcr7 bit name os3 to os0 pcr76 pin function setting value 0000 0 p76 input pin 1 p76 output pin other than the above values x tmov output pin legend x: don't care. p75/tmciv pin register pcr7 bit name pcr75 pin function setting value 0 p75 input/tmciv input pin 1 p75 output/tmciv input pin p74/tmriv pin register pcr7 bit name pcr74 pin function setting value 0 p74 input/tmriv input pin 1 p74 output/tmriv input pin rev. 2.0, 03/02, page 106 of 298 9.5 port 8 port 8 is a general i/o port also functioning as a timer w i/o pin. each pin of the port 8 is shown in figure 9.5. the register setting of the timer w has priority for functions of the pins p84/ftiod, p83/ftioc, p82/ftiob, and p81/ftioa. the p80/ftci pin also functions as a timer w input port that is connected to the timer w regardless of the register setting of port 8. p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci port 8 figure 9.5 port 8 pin configuration port 8 has the following registers. port control register 8 (pcr8) port data register 8 (pdr8) 9.5.1 port control register 8 (pcr8) pcr8 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 8. bit bit name initial value r/w description 7 6 5 ? ? ? ? ? ? ? ? ? reserved 4 3 2 1 0 pcr84 pcr83 pcr82 pcr81 pcr80 0 0 0 0 0 w w w w w when each of the port 8 pins p84 to p80 functions as an general i/o port, setting a pcr8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. rev. 2.0, 03/02, page 107 of 298 9.5.2 port data register 8 (pdr8) pdr8 is a general i/o port data register of port 8. bit bit name initial value r/w description 7 6 5 ? ? ? 0 0 0 ? ? ? reserved 4 3 2 1 0 p84 p83 p82 p81 p80 0 0 0 0 0 r/w r/w r/w r/w r/w pdr8 stores output data for port 8 pins. if pdr8 is read while pcr8 bits are set to 1, the value stored in pdr8 is read. if pdr8 is read while pcr8 bits are cleared to 0, the pin states are read regardless of the value stored in pdr8. 9.5.3 pin functions the correspondence between the register specification and the port functions is shown below. p84/ftiod pin register tior1 pcr8 bit name iod2 iod1 iod0 pcr84 pin function setting value0000p84 input/ftiod input pin 1 p84 output/ftiod input pin 0 0 1 x ftiod output pin 0 1 x x ftiod output pin 1 x x 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin legend x: don't care. rev. 2.0, 03/02, page 108 of 298 p83/ftioc pin register tior1 pcr8 bit name ioc2 ioc1 ioc0 pcr83 pin function setting value0000p83 input/ftioc input pin 1 p83 output/ftioc input pin 0 0 1 x ftioc output pin 0 1 x x ftioc output pin 1 x x 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin legend x: don't care. p82/ftiob pin register tior0 pcr8 bit name iob2 iob1 iob0 pcr82 pin function setting value0000p82 input/ftiob input pin 1 p82 output/ftiob input pin 0 0 1 x ftiob output pin 0 1 x x ftiob output pin 1 x x 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin legend x: don't care. p81/ftioa pin register tior0 pcr8 bit name ioa2 ioa1 ioa0 pcr81 pin function setting value0000p81 input/ftioa input pin 1 p81 output/ftioa input pin 0 0 1 x ftioa output pin 0 1 x x ftioa output pin 1 x x 0 p81 input/ftioa input pin 1 p81 output/ftioa input pin legend x: don't care. rev. 2.0, 03/02, page 109 of 298 p80/ftci pin register pcr8 bit name pcr80 pin function setting value 0 p80 input/ftci input pin 1 p80 output/ftci input pin 9.6 port b port b is an input port also functioning as an a/d converter analog input pin. each pin of the port b is shown in figure 9.6. pb3/an3 pb2/an2 pb1/an1 pb0/an0 port b figure 9.6 port b pin configuration port b has the following register. port data register b (pdrb) rev. 2.0, 03/02, page 110 of 298 9.6.1 port data register b (pdrb) pdrb is a general input-only port data register of port b. bit bit name initial value r/w description 7 6 5 4 ? ? ? ? ? ? ? ? ? ? ? ? reserved 3 2 1 0 pb3 pb2 pb1 pb0 ? ? ? ? r r r r the input value of each pin is read by reading this register. however, if a port b pin is designated as an analog input channel by adcsr in a/d converter, 0 is read. rev. 2.0, 03/02, page 111 of 298 section 10 timer v timer v is an 8-bit timer based on an 8-bit counter. timer v counts external events. compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. counting can be initiated by a trigger input at the trgv pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. figure 10.1 shows a block diagram of timer v. 10.1 features choice of seven clock signals is available. choice of six internal clock sources (?/128, ?/64, ?/32, ?/16, ?/8, ?/4) or an external clock. counter can be cleared by compare match a or b, or by an external reset signal. if the count stop function is selected, the counter can be halted when cleared. timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, pwm output, and other applications. three interrupt sources: compare match a, compare match b, timer overflow counting can be initiated by trigger input at the trgv pin. the rising edge, falling edge, or both edges of the trgv input can be selected. tim08v0a_000020020300 rev. 2.0, 03/02, page 112 of 298 trgv tmciv tmriv tmov ? trigger control clock select clear control output control pss tcrv1 tcorb comparator tcntv comparator tcora tcrv0 interrupt request control tcsrv cmia cmib ovi internal data bus legend : tcora: time constant register a tcorb: time constant register b tcntv: timer counter v tcsrv: timer control/status register v tcrv0: timer control register v0 tcrv1: timer control register v1 pss: prescaler s cmia: compare-match interrupt a cmib: compare-match interrupt b ovi: overflow interupt figure 10.1 block diagram of timer v 10.2 input/output pins table 10.1 shows the timer v pin configuration. table 10.1 pin configuration name abbreviation i/o function timer v output tmov output timer v waveform output timer v clock input tmciv input clock input to tcntv timer v reset input tmriv input external input to reset tcntv trigger input trgv input trigger input to initiate counting rev. 2.0, 03/02, page 113 of 298 10.3 register descriptions time v has the following registers. timer counter v (tcntv) timer constant register a (tcora) timer constant register b (tcorb) timer control register v0 (tcrv0) timer control/status register v (tcsrv) timer control register v1 (tcrv1) 10.3.1 timer counter v (tcntv) tcntv is an 8-bit up-counter. the clock source is selected by bits cks2 to cks0 in timer control register v0 (tcrv0). the tcntv value can be read and written by the cpu at any time. tcntv can be cleared by an external reset input signal, or by compare match a or b. the clearing signal is selected by bits cclr1 and cclr0 in tcrv0. when tcntv overflows, ovf is set to 1 in timer control/status register v (tcsrv). tcntv is initialized to h'00. 10.3.2 time constant registers a and b (tcora, tcorb) tcora and tcorb have the same function. tcora and tcorb are 8-bit read/write registers. tcora and tcntv are compared at all times. when the tcora and tcntv contents match, cmfa is set to 1 in tcsrv. if cmiea is also set to 1 in tcrv0, a cpu interrupt is requested. note that they must not be compared during the t3 state of a tcora write cycle. timer output from the tmov pin can be controlled by the identifying signal (compare match a) and the settings of bits os3 to os0 in tcsrv. tcora and tcorb are initialized to h'ff. rev. 2.0, 03/02, page 114 of 298 10.3.3 timer control register v0 (tcrv0) tcrv0 selects the input clock signals of tcntv, specifies the clearing conditions of tcntv, and controls each interrupt request. bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b when this bit is set to 1, interrupt request from the cmfb bit in tcsrv is enabled. 6 cmiea 0 r/w compare match interrupt enable a when this bit is set to 1, interrupt request from the cmfa bit in tcsrv is enabled. 5 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, interrupt request from the ovf bit in tcsrv is enabled. 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits specify the clearing conditions of tcntv. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared on the rising edge of the tmriv pin. the operation of tcntv after clearing depends on trge in tcrv1. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select clock signals to input to tcntv and the counting condition in combination with icks0 in tcrv1. refer to table 10.2. rev. 2.0, 03/02, page 115 of 298 table 10.2 clock signals to input to tcntv and counting conditions tcrv0 tcrv1 bit 2 bit 1 bit 0 bit 0 cks2 cks1 cks0 icks0 description 000 ? clock input prohibited 1 0 internal clock: counts on f /4, falling edge 1 internal clock: counts on f /8, falling edge 1 0 0 internal clock: counts on f /16, falling edge 1 internal clock: counts on f /32, falling edge 1 0 internal clock: counts on f /64, falling edge 1 internal clock: counts on f /128, falling edge 100 ? clock input prohibited 1 ? external clock: counts on rising edge 10 ? external clock: counts on falling edge 1 ? external clock: counts on rising and falling edge rev. 2.0, 03/02, page 116 of 298 10.3.4 timer control/status register v (tcsrv) tcsrv indicates the status flag and controls outputs by using a compare match. bit bit name initial value r/w description 7 cmfb 0 r/w compare match flag b setting condition: when the tcntv value matches the tcorb value clearing condition: after reading cmfb = 1, cleared by writing 0 to cmfb 6 cmfa 0 r/w compare match flag a setting condition: when the tcntv value matches the tcora value clearing condition: after reading cmfa = 1, cleared by writing 0 to cmfa 5 ovf 0 r/w timer overflow flag setting condition: when tcntv overflows from h'ff to h'00 clearing condition: after reading ovf = 1, cleared by writing 0 to ovf 4 ? 1 ? reserved this bit is always read as 1. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits select an output method for the tomv pin by the compare match of tcorb and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits select an output method for the tomv pin by the compare match of tcora and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles rev. 2.0, 03/02, page 117 of 298 os3 and os2 select the output level for compare match b. os1 and os0 select the output level for compare match a. the two output levels can be controlled independently. after a reset, the timer output is 0 until the first compare match. 10.3.5 timer control register v1 (tcrv1) tcrv1 selects the edge at the trgv pin, enables trgv input, and selects the clock input to tcntv. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 tveg1 tveg0 0 0 r/w r/w trgv input edge select these bits select the trgv input edge. 00: trgv trigger input is prohibited 01: rising edge is selected 10: falling edge is selected 11: rising and falling edges are both selected 2 trge 0 r/w tcntv starts counting up by the input of the edge which is selected by tveg1 and tveg0. 0: disables starting counting-up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1: enables starting counting-up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1 ? 1 ? reserved this bit is always read as 1. 0 icks0 0 r/w internal clock select 0 this bit selects clock signals to input to tcntv in combination with cks2 to cks0 in tcrv0. refer to table 10.2. rev. 2.0, 03/02, page 118 of 298 10.4 operation 10.4.1 timer v operation 1. according to table 10.2, six internal/external clock signals output by prescaler s can be selected as the timer v operating clock signals. when the operating clock signal is selected, tcntv starts counting-up. figure 10.2 shows the count timing with an internal clock signal selected, and figure 10.3 shows the count timing with both edges of an external clock signal selected. 2. when tcntv overflows (changes from h'ff to h'00), the overflow flag (ovf) in tcrv0 will be set. the timing at this time is shown in figure 10.4. an interrupt request is sent to the cpu when ovie in tcrv0 is 1. 3. tcntv is constantly compared with tcora and tcorb. compare match flag a or b (cmfa or cmfb) is set to 1 when tcntv matches tcora or tcorb, respectively. the compare-match signal is generated in the last state in which the values match. figure 10.5 shows the timing. an interrupt request is generated for the cpu when cmiea or cmieb in tcrv0 is 1. 4. when a compare match a or b is generated, the tmov responds with the output value selected by bits os3 to os0 in tcsrv. figure 10.6 shows the timing when the output is toggled by compare match a. 5. when cclr1 or cclr0 in tcrv0 is 01 or 10, tcntv can be cleared by the corresponding compare match. figure 10.7 shows the timing. 6. when cclr1 or cclr0 in tcrv0 is 11, tcntv can be cleared by the rising edge of the input of tmriv pin. a tmriv input pulse-width of at least 1.5 system clocks is necessary. figure 10.8 shows the timing. 7. when a counter-clearing source is generated with trge in tcrv1 set to 1, the counting-up is halted as soon as tcntv is cleared. tcntv resumes counting-up when the edge selected by tveg1 or tveg0 in tcrv1 is input from the tgrv pin. n C 1 n + 1 n ? internal clock tcntv input clock tcntv figure 10.2 increment timing with internal clock rev. 2.0, 03/02, page 119 of 298 n C 1 n + 1 n ? tmciv (external clock input pin) tcntv input clock tcntv figure 10.3 increment timing with external clock h'ff h'00 ? tcntv overflow signal ovf figure 10.4 ovf set timing n n n+1 ? tcntv tcora or tcorb compare match signal cmfa or cmfb figure 10.5 cmfa and cmfb set timing rev. 2.0, 03/02, page 120 of 298 ? compare match a signal timer v output pin figure 10.6 tmov output timing n h'00 ? compare match a signal tcntv figure 10.7 clear timing by compare match n C 1 n h'00 ? compare match a signal timer v output pin tcntv figure 10.8 clear timing by tmriv input rev. 2.0, 03/02, page 121 of 298 10.5 timer v application examples 10.5.1 pulse output with arbitrary duty cycle figure 10.9 shows an example of output of pulses with an arbitrary duty cycle. 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcora. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 4. with these settings, a waveform is output without further software intervention, with a period determined by tcora and a pulse width determined by tcorb. counter cleared time tcntv value h'ff tcora tcorb h'00 tmov figure 10.9 pulse output example rev. 2.0, 03/02, page 122 of 298 10.5.2 pulse output with arbitrary pulse width and delay from trgv input the trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the trgv input, as shown in figure 10.10. to set up this output: 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcorb. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits tveg1 and tveg0 in tcrv1 and set trge to select the falling edge of the trgv input. 4. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 5. after these settings, a pulse waveform will be output without further software intervention, with a delay determined by tcora from the trgv input, and a pulse width determined by (tcorb C tcora). counter cleared h'ff tcora tcorb h'00 trgv tmov compare match a compare match b clears tcntv and halts count-up compare match b clears tcntv and halts count-up compare match a tcntv value time figure 10.10 example of pulse output synchronized to trgv input rev. 2.0, 03/02, page 123 of 298 10.6 usage notes the following types of contention or operation can occur in timer v operation. 1. writing to registers is performed in the t3 state of a tcntv write cycle. if a tcntv clear signal is generated in the t3 state of a tcntv write cycle, as shown in figure 10.11, clearing takes precedence and the write to the counter is not carried out. if counting-up is generated in the t3 state of a tcntv write cycle, writing takes precedence. 2. if a compare match is generated in the t3 state of a tcora or tcorb write cycle, the write to tcora or tcorb takes precedence and the compare match signal is inhibited. figure 10.12 shows the timing. 3. if compare matches a and b occur simultaneously, any conflict between the output selections for compare match a and compare match b is resolved by the following priority: toggle output > output 1 > output 0. 4. depending on the timing, tcntv may be incremented by a switch between different internal clock sources. when tcntv is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock ( f ). therefore, as shown in figure 10.3 the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing tcntv to increment. tcntv can also be incremented by a switch between internal and external clocks. ? address tcntv address tcntv write cycle by cpu internal write signal counter clear signal tcntv n h'00 t 1 t 2 t 3 figure 10.11 contention between tcntv write and clear rev. 2.0, 03/02, page 124 of 298 ? address tcora address internal write signal tcntv tcora n n n+1 m tcora write data inhibited t 1 t 2 t 3 tcora write cycle by cpu compare match signal figure 10.12 contention between tcora write and compare match clock before switching clock after switching count clock tcntv n n+1 n+2 write to cks1 and cks0 figure 10.13 internal clock switching and tcntv operation rev. 2.0, 03/02, page 125 of 298 section 11 timer w the timer w has a 16-bit timer having output compare and input capture functions. the timer w can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. thus, it can be applied to various systems. 11.1 features selection of five counter clock sources: four internal clocks ( f , f /2, f /4, and f /8) and an external clock (external events can be counted) capability to process up to four pulse outputs or four pulse inputs four general registers: ? independently assignable output compare or input capture functions ? usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register four selectable operating modes : ? waveform output by compare match selection of 0 output, 1 output, or toggle output ? input capture function rising edge, falling edge, or both edges ? counter clearing function counters can be cleared by compare match ? pwm mode up to three-phase pwm output can be provided with desired duty ratio. any initial timer output value can be set five interrupt sources four compare match/input capture interrupts and an overflow interrupt. table 11.1 summarizes the timer w functions, and figure 11.1 shows a block diagram of the timer w. tim08w0a_000020020300 rev. 2.0, 03/02, page 126 of 298 table 11.1 timer w functions input/output pins item counter ftioa ftiob ftioc ftiod count clock internal clocks: f , f /2, f /4, f /8 external clock: ftci general registers (output compare/input capture registers) period specified in gra gra grb grc (buffer register for gra in buffer mode) grd (buffer register for grb in buffer mode) counter clearing function gra compare match gra compare match initial output value setting function yes yes yes yes buffer function yes yes compare 0 yes yes yes yes match output 1 yes yes yes yes toggle yes yes yes yes input capture function yes yes yes yes pwm mode yes yes yes interrupt sources overflow compare match/input capture compare match/input capture compare match/input capture compare match/input capture rev. 2.0, 03/02, page 127 of 298 internal clock: external clock: ftci ftioa ftiob ftioc ftiod irrtw control logic clock selector comparator tcnt internal data bus bus interface legend : tmrw: timer mode register w (8 bits) tcrw: timer control register w (8 bits) tierw: timer interrupt enable register w (8 bits) tsrw: timer status register w (8 bits) tior: timer i/o control register (8 bits) tcnt: timer counter (16 bits) gra: general register a (input capture/output compare register: 16 bits) grb: general register b (input capture/output compare register: 16 bits) grc: general register c (input capture/output compare register: 16 bits) grd: general register d (input capture/output compare register: 16 bits) irrtw: timer w interrupt request gra grb grc grd tmrw tcrw tierw tsrw tior ? ?/2 ?/4 ?/8 figure 11.1 timer w block diagram 11.2 input/output pins table 11.2 summarizes the timer w pins. table 11.2 pin configuration name abbreviation input/output function external clock input ftci input external clock input pin input capture/output compare a ftioa input/output output pin for gra output compare or input pin for gra input capture input capture/output compare b ftiob input/output output pin for grb output compare, input pin for grb input capture, or pwm output pin in pwm mode input capture/output compare c ftioc input/output output pin for grc output compare, input pin for grc input capture, or pwm output pin in pwm mode input capture/output compare d ftiod input/output output pin for grd output compare, input pin for grd input capture, or pwm output pin in pwm mode rev. 2.0, 03/02, page 128 of 298 11.3 register descriptions the timer w has the following registers. timer mode register w (tmrw) timer control register w (tcrw) timer interrupt enable register w (tierw) timer status register w (tsrw) timer i/o control register 0 (tior0) timer i/o control register 1 (tior1) timer counter (tcnt) general register a (gra) general register b (grb) general register c (grc) general register d (grd) rev. 2.0, 03/02, page 129 of 298 11.3.1 timer mode register w (tmrw) tmrw selects the general register functions and the timer output mode. bit bit name initial value r/w description 7 cts 0 r/w counter start the counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 ? 1 ? reserved this bit is always read as 1. 5 bufeb 0 r/w buffer operation b selects the grd function. 0: grd operates as an input capture/output compare register 1: grd operates as the buffer register for grb 4 bufea 0 r/w buffer operation a selects the grc function. 0: grc operates as an input capture/output compare register 1: grc operates as the buffer register for gra 3 ? 1 ? reserved this bit is always read as 1. 2 pwmd 0 r/w pwm mode d selects the output mode of the ftiod pin. 0: ftiod operates normally (output compare output) 1: pwm output 1 pwmc 0 r/w pwm mode c selects the output mode of the ftioc pin. 0: ftioc operates normally (output compare output) 1: pwm output 0 pwmb 0 r/w pwm mode b selects the output mode of the ftiob pin. 0: ftiob operates normally (output compare output) 1: pwm output 11.3.2 timer control register w (tcrw) tcrw selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. rev. 2.0, 03/02, page 130 of 298 bit bit name initial value r/w description 7 cclr 0 r/w counter clear the tcnt value is cleared by compare match a when this bit is 1. when it is 0, tcnt operates as a free-running counter. 6 5 4 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select the tcnt clock source. 000: internal clock: counts on f 001: internal clock: counts on f /2 010: internal clock: counts on f /4 011: internal clock: counts on f /8 1xx: counts on rising edges of the external event (ftci) when the internal clock source ( f ) is selected, subclock sources are counted in subactive and subsleep modes. 3 tod 0 r/w timer output level setting d 0: output value is 0 * 1: output value is 1 * 2 toc 0 r/w timer output level setting c 0: output value is 0 * 1: output value is 1 * 1 tob 0 r/w timer output level setting b 0: output value is 0 * 1: output value is 1 * 0 toa 0 r/w timer output level setting a 0: output value is 0 * 1: output value is 1 * legend x: don't care. note: * the change of the setting is immediately reflected in the output value. rev. 2.0, 03/02, page 131 of 298 11.3.3 timer interrupt enable register w (tierw) tierw controls the timer w interrupt request. bit bit name initial value r/w description 7 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, fovi interrupt requested by ovf flag in tsrw is enabled. 6 5 4 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 3 imied 0 r/w input capture/compare match interrupt enable d when this bit is set to 1, imid interrupt requested by imfd flag in tsrw is enabled. 2 imiec 0 r/w input capture/compare match interrupt enable c when this bit is set to 1, imic interrupt requested by imfc flag in tsrw is enabled. 1 imieb 0 r/w input capture/compare match interrupt enable b when this bit is set to 1, imib interrupt requested by imfb flag in tsrw is enabled. 0 imiea 0 r/w input capture/compare match interrupt enable a when this bit is set to 1, imia interrupt requested by imfa flag in tsrw is enabled. 11.3.4 timer status register w (tsrw) tsrw shows the status of interrupt requests. bit bit name initial value r/w description 7 ovf 0 r/w timer overflow flag [setting condition] when tcnt overflows from h'ffff to h'0000 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 6 5 4 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. rev. 2.0, 03/02, page 132 of 298 bit bit name initial value r/w description 3 imfd 0 r/w input capture/compare match flag d [setting conditions] tcnt = grd when grd functions as an output compare register the tcnt value is transferred to grd by an input capture signal when grd functions as an input capture register [clearing condition] read imfd when imfd = 1, then write 0 in imfd 2 imfc 0 r/w input capture/compare match flag c [setting conditions] tcnt = grc when grc functions as an output compare register the tcnt value is transferred to grc by an input capture signal when grc functions as an input capture register [clearing condition] read imfc when imfc = 1, then write 0 in imfc 1 imfb 0 r/w input capture/compare match flag b [setting conditions] tcnt = grb when grb functions as an output compare register the tcnt value is transferred to grb by an input capture signal when grb functions as an input capture register [clearing condition] read imfb when imfb = 1, then write 0 in imfb 0 imfa 0 r/w input capture/compare match flag a [setting conditions] tcnt = gra when gra functions as an output compare register the tcnt value is transferred to gra by an input capture signal when gra functions as an input capture register [clearing condition] read imfa when imfa = 1, then write 0 in imfa rev. 2.0, 03/02, page 133 of 298 11.3.5 timer i/o control register 0 (tior0) tior0 selects the functions of gra and grb, and specifies the functions of the ftioa and ftiob pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iob2 0 r/w i/o control b2 selects the grb function. 0: grb functions as an output compare register 1: grb functions as an input capture register 5 4 iob1 iob0 0 0 r/w r/w i/o control b1 and b0 when iob2 = 0, 00: no output at compare match 01: 0 output to the ftiob pin at grb compare match 10: 1 output to the ftiob pin at grb compare match 11: output toggles to the ftiob pin at grb compare match when iob2 = 1, 00: input capture at rising edge at the ftiob pin 01: input capture at falling edge at the ftiob pin 1x: input capture at rising and falling edges of the ftiob pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioa2 0 r/w i/o control a2 selects the gra function. 0: gra functions as an output compare register 1: gra functions as an input capture register 1 0 ioa1 ioa0 0 0 r/w r/w i/o control a1 and a0 when ioa2 = 0, 00: no output at compare match 01: 0 output to the ftioa pin at gra compare match 10: 1 output to the ftioa pin at gra compare match 11: output toggles to the ftioa pin at gra compare match when ioa2 = 1, 00: input capture at rising edge of the ftioa pin 01: input capture at falling edge of the ftioa pin 1x: input capture at rising and falling edges of the ftioa pin legend x: don't care. rev. 2.0, 03/02, page 134 of 298 11.3.6 timer i/o control register 1 (tior1) tior1 selects the functions of grc and grd, and specifies the functions of the ftioc and ftiod pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iod2 0 r/w i/o control d2 selects the grd function. 0: grd functions as an output compare register 1: grd functions as an input capture register 5 4 iod1 iod0 0 0 r/w r/w i/o control d1 and d0 when iod2 = 0, 00: no output at compare match 01: 0 output to the ftiod pin at grd compare match 10: 1 output to the ftiod pin at grd compare match 11: output toggles to the ftiod pin at grd compare match when iod2 = 1, 00: input capture at rising edge at the ftiod pin 01: input capture at falling edge at the ftiod pin 1x: input capture at rising and falling edges at the ftiod pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioc2 0 r/w i/o control c2 selects the grc function. 0: grc functions as an output compare register 1: grc functions as an input capture register 1 0 ioc1 ioc0 0 0 r/w r/w i/o control c1 and c0 when ioc2 = 0, 00: no output at compare match 01: 0 output to the ftioc pin at grc compare match 10: 1 output to the ftioc pin at grc compare match 11: output toggles to the ftioc pin at grc compare match when ioc2 = 1, 00: input capture to grc at rising edge of the ftioc pin 01: input capture to grc at falling edge of the ftioc pin 1x: input capture to grc at rising and falling edges of the ftioc pin legend x: don't care. rev. 2.0, 03/02, page 135 of 298 11.3.7 timer counter (tcnt) tcnt is a 16-bit readable/writable up-counter. the clock source is selected by bits cks2 to cks0 in tcrw. tcnt can be cleared to h'0000 through a compare match with gra by setting the cclr in tcrw to 1. when tcnt overflows (changes from h'ffff to h'0000), the ovf flag in tsrw is set to 1. if ovie in tierw is set to 1 at this time, an interrupt request is generated. tcnt must always be read or written in 16-bit units; 8-bit access is not allowed. tcnt is initialized to h'0000 by a reset. 11.3.8 general registers a to d (gra to grd) each general register is a 16-bit readable/writable register that can function as either an output- compare register or an input-capture register. the function is selected by settings in tior0 and tior1. when a general register is used as an input-compare register, its value is constantly compared with the tcnt value. when the two values match (a compare match), the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. an interrupt request is generated at this time, when imiea, imieb, imiec, or imied is set to 1. compare match output can be selected in tior. when a general register is used as an input-capture register, an external input-capture signal is detected and the current tcnt value is stored in the general register. the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. if the corresponding interrupt-enable bit (imiea, imieb, imiec, or imied) in tsrw is set to 1 at this time, an interrupt request is generated. the edge of the input-capture signal is selected in tior. grc and grd can be used as buffer registers of gra and grb, respectively, by setting bufea and bufeb in tmrw. for example, when gra is set as an output-compare register and grc is set as the buffer register for gra, the value in the buffer register grc is sent to gra whenever compare match a is generated. when gra is set as an input-capture register and grc is set as the buffer register for gra, the value in tcnt is transferred to gra and the value in the buffer register grc is transferred to gra whenever an input capture is generated. gra to grd must be written or read in 16-bit units; 8-bit access is not allowed. gra to grd are initialized to h'ffff by a reset. rev. 2.0, 03/02, page 136 of 298 11.4 operation the timer w has the following operating modes. normal operation pwm operation 11.4.1 normal operation tcnt performs free-running or periodic counting operations. after a reset, tcnt is set as a free- running counter. when the cst bit in tmrw is set to 1, tcnt starts incrementing the count. when the count overflows from h'ffff to h'0000, the ovf flag in tsrw is set to 1. if the ovie in tierw is set to 1, an interrupt request is generated. figure 11.2 shows free-running counting. tcnt value h'ffff h'0000 cst bit ovf time flag cleared by software figure 11.2 free-running counter operation periodic counting operation can be performed when gra is set as an output compare register and bit cclr in tcrw is set to 1. when the count matches gra, tcnt is cleared to h'0000, the imfa flag in tsrw is set to 1. if the corresponding imiea bit in tierw is set to 1, an interrupt request is generated. tcnt continues counting from h'0000. figure 11.3 shows periodic counting. rev. 2.0, 03/02, page 137 of 298 tcnt value gra h'0000 cst bit imfa time flag cleared by software figure 11.3 periodic counter operation by setting a general register as an output compare register, compare match a, b, c, or d can cause the output at the ftioa, ftiob, ftioc, or ftiod pin to output 0, output 1, or toggle. figure 11.4 shows an example of 0 and 1 output when tcnt operates as a free-running counter, 1 output is selected for compare match a, and 0 output is selected for compare match b. when signal is already at the selected output level, the signal level does not change at compare match. tcnt value h'ffff h'0000 ftioa ftiob time gra grb no change no change no change no change figure 11.4 0 and 1 output example (toa = 0, tob = 1) figure 11.5 shows an example of toggle output when tcnt operates as a free-running counter, and toggle output is selected for both compare match a and b. rev. 2.0, 03/02, page 138 of 298 tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output figure 11.5 toggle output example (toa = 0, tob = 1) figure 11.6 shows another example of toggle output when tcnt operates as a periodic counter, cleared by compare match a. toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output counter cleared by compare match with gra figure 11.6 toggle output example (toa = 0, tob = 1) the tcnt value can be captured into a general register (gra, grb, grc, or grd) when a signal level changes at an input-capture pin (ftioa, ftiob, ftioc, or ftiod). capture can take place on the rising edge, falling edge, or both edges. by using the input-capture function, the pulse width and periods can be measured. figure 11.7 shows an example of input capture when both edges of ftioa and the falling edge of ftiob are selected as capture edges. tcnt operates as a free-running counter. rev. 2.0, 03/02, page 139 of 298 tcnt value h'ffff h'1000 h'0000 ftioa gra time h'aa55 h'55aa h'f000 h'1000 h'f000 h'55aa grb h'aa55 ftiob figure 11.7 input capture operating example figure 11.8 shows an example of buffer operation when the gra is set as an input-capture register and grc is set as the buffer register for gra. tcnt operates as a free-running counter, and ftioa captures both rising and falling edge of the input signal. due to the buffer operation, the gra value is transferred to grc by input-capture a and the tcnt value is stored in gra. tcnt value h'da91 h'0245 h'0000 grc time h'0245 ftioa gra h'5480 h'0245 h'ffff h'5480 h'5480 h'da91 figure 11.8 buffer operation example (input capture) rev. 2.0, 03/02, page 140 of 298 11.4.2 pwm operation in pwm mode, pwm waveforms are generated by using gra as the period register and grb, grc, and grd as duty registers. pwm waveforms are output from the ftiob, ftioc, and ftiod pins. up to three-phase pwm waveforms can be output. in pwm mode, a general register functions as an output compare register automatically. the output level of each pin depends on the corresponding timer output level set bit (tob, toc, and tod) in tcrw. when tob is 1, the ftiob output goes to 1 at compare match a and to 0 at compare match b. when tob is 0, the ftiob output goes to 0 at compare match a and to 1 at compare match b. thus the compare match output level settings in tior0 and tior1 are ignored for the output pin set to pwm mode. if the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. figure 11.9 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is cleared at compare match a, and the output signals go to 0 at compare match b, c, and d (tob, toc, and tod = 1: initial output values are set to 1). tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 11.9 pwm mode example (1) figure 11.10 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is cleared at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0: initial output values are set to 1). rev. 2.0, 03/02, page 141 of 298 tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 11.10 pwm mode example (2) figure 11.11 shows an example of buffer operation when the ftiob pin is set to pwm mode and grd is set as the buffer register for grb. tcnt is cleared by compare match a, and ftiob outputs 1 at compare match b and 0 at compare match a. due to the buffer operation, the ftiob output level changes and the value of buffer register grd is transferred to grb whenever compare match b occurs. this procedure is repeated every time compare match b occurs. tcnt value gra h'0000 grd time grb h'0200 h'0520 ftiob h'0200 h'0450 h'0520 h'0450 grb h'0450 h'0520 h'0200 figure 11.11 buffer operation example (output compare) figures 11.12 and 11.13 show examples of the output of pwm waveforms with duty cycles of 0% and 100%. rev. 2.0, 03/02, page 142 of 298 tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 0% write to grb figure 11.12 pwm mode example (tob, toc, and tod = 0: initial output values are set to 0) rev. 2.0, 03/02, page 143 of 298 tcnt value gra h'0000 ftiob time grb duty 100% write to grb tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 100% write to grb write to grb write to grb figure 11.13 pwm mode example (tob, toc, and tod = 1: initial output values are set to 1) rev. 2.0, 03/02, page 144 of 298 11.5 operation timing 11.5.1 tcnt count timing figure 11.14 shows the tcnt count timing when the internal clock source is selected. figure 11.15 shows the timing when the external clock source is selected. the pulse width of the external clock signal must be at least two system clock ( f ) cycles; shorter pulses will not be counted correctly. tcnt tcnt input clock internal clock f n n+1 n+2 rising edge figure 11.14 count timing for internal clock source tcnt tcnt input clock external clock f n n+1 n+2 rising edge rising edge figure 11.15 count timing for external clock source 11.5.2 output compare output timing the compare match signal is generated in the last state in which tcnt and gr match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches gr, the compare match signal is generated only after the next counter clock pulse is input. rev. 2.0, 03/02, page 145 of 298 figure 11.16 shows the output compare timing. gra to grd tcnt tcnt input clock f n n n+1 compare match signal ftioa to ftiod figure 11.16 output compare output timing 11.5.3 input capture timing input capture on the rising edge, falling edge, or both edges can be selected through settings in tior0 and tior1. figure 11.17 shows the timing when the falling edge is selected. the pulse width of the input capture signal must be at least two system clock ( f ) cycles; shorter pulses will not be detected correctly. tcnt input capture input ? nC1 n n+1 n+2 n gra to grd input capture signal figure 11.17 input capture input signal timing rev. 2.0, 03/02, page 146 of 298 11.5.4 timing of counter clearing by compare match figure 11.18 shows the timing when the counter is cleared by compare match a. when the gra value is n, the counter counts from 0 to n, and its cycle is n + 1. tcnt compare match signal f gra n n h'0000 figure 11.18 timing of counter clearing by compare match 11.5.5 buffer operation timing figures 11.19 and 11.20 show the buffer operation timing. grc, grd compare match signal tcnt f gra, grb n n+1 m m figure 11.19 buffer operation timing (compare match) rev. 2.0, 03/02, page 147 of 298 gra, grb tcnt input capture signal f grc, grd n m m n+1 n n n+1 figure 11.20 buffer operation timing (input capture) 11.5.6 timing of imfa to imfd flag setting at compare match if a general register (gra, grb, grc, or grd) is used as an output compare register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when tcnt matches the general register. the compare match signal is generated in the last state in which the values match (when tcnt is updated from the matching count to the next count). therefore, when tcnt matches a general register, the compare match signal is generated only after the next tcnt clock pulse is input. figure 11.21 shows the timing of the imfa to imfd flag setting at compare match. gra to grd tcnt tcnt input clock f n n n+1 compare match signal imfa to imfd irrtw figure 11.21 timing of imfa to imfd flag setting at compare match rev. 2.0, 03/02, page 148 of 298 11.5.7 timing of imfa to imfd setting at input capture if a general register (gra, grb, grc, or grd) is used as an input capture register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when an input capture occurs. figure 11.22 shows the timing of the imfa to imfd flag setting at input capture. gra to grd tcnt input capture signal f n n imfa to imfd irrtw figure 11.22 timing of imfa to imfd flag setting at input capture 11.5.8 timing of status flag clearing when the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 11.23 shows the status flag clearing timing. imfa to imfd write signal address f tsrw address irrtw tsrw write cycle t1 t2 figure 11.23 timing of status flag clearing by cpu rev. 2.0, 03/02, page 149 of 298 11.6 usage notes the following types of contention or operation can occur in timer w operation. 1. the pulse width of the input clock signal and the input capture signal must be at least two system clock ( f ) cycles; shorter pulses will not be detected correctly. 2. writing to registers is performed in the t2 state of a tcnt write cycle. if counter clear signal occurs in the t2 state of a tcnt write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 11.24. if counting-up is generated in the tcnt write cycle to contend with the tcnt counting-up, writing takes precedence. 3. depending on the timing, tcnt may be incremented by a switch between different internal clock sources. when tcnt is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is divided system clock ( f ). therefore, as shown in figure 11.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing tcnt to increment. 4. if timer w enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. before entering module standby mode, disable interrupt requests. counter clear signal write signal address f tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 11.24 contention between tcnt write and clear rev. 2.0, 03/02, page 150 of 298 tcnt previous clock n n+1 n+2 n+3 new clock count clock the change in signal level at clock switching is assumed to be a rising edge, and tcnt increments the count. figure 11.25 internal clock switching and tcnt operation rev. 2.0, 03/02, page 151 of 298 section 12 watchdog timer the watchdog timer is an 8-bit timer that can generate an internal reset signal for this lsi if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. the block diagram of the watchdog timer is shown in figure 12.1. ? internal reset signal pss tcwd tmwd tcsrwd internal data bus legend : tcsrwd: timer control/status register wd tcwd: timer counter wd pss: prescaler s tmwd: timer mode register wd internal oscillator clk figure 12.1 block diagram of watchdog timer 12.1 features selectable from nine counter input clocks. eight clock sources ( f /64, f /128, f /256, f /512, f /1024, f /2048, f /4096, and f /8192) or the internal oscillator can be selected as the timer-counter clock. when the internal oscillator is selected, it can operate as the watchdog timer in any operating mode. reset signal generated on counter overflow an overflow period of 1 to 256 times the selected clock can be set. 12.2 register descriptions the watchdog timer has the following registers. timer control/status register wd (tcsrwd) timer counter wd (tcwd) timer mode register wd (tmwd) wdt0110a_000020020300 rev. 2.0, 03/02, page 152 of 298 12.2.1 timer control/status register wd (tcsrwd) tcsrwd performs the tcsrwd and tcwd write control. tcsrwd also controls the watchdog timer operation and indicates the operating state. tcsrwd must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 b6wi 1 r/w bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6 tcwe 0 r/w timer counter wd write enable tcwd can be written when the tcwe bit is set to 1. when writing data to this bit, the value for bit 7 must be 0. 5 b4wi 1 r/w bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/w timer control/status register w write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 3 b2wi 1 r/w bit 2 write inhibit this bit can be written to the wdon bit only when the write value of the b2wi bit is 0. this bit is always read as 1. 2 wdon 0 r/w watchdog timer on tcwd starts counting up when wdon is set to 1 and halts when wdon is cleared to 0. [setting condition] when 1 is written to the wdon bit while writing 0 to the b2wi bit when the tcsrwe bit=1 [clearing condition] reset by 5(6 pin when 0 is written to the wdon bit while writing 0 to the b2wi when the tcsrwe bit=1 1 b0wi 1 r/w bit 0 write inhibit this bit can be written to the wrst bit only when the write value of the b0wi bit is 0. this bit is always read as 1. rev. 2.0, 03/02, page 153 of 298 bit bit name initial value r/w description 0 wrst 0 r/w watchdog timer reset [setting condition] when tcwd overflows and an internal reset signal is generated [clearing condition] reset by 5(6 pin when 0 is written to the wrst bit while writing 0 to the b0wi bit when the tcsrwe bit=1 12.2.2 timer counter wd (tcwd) tcwd is an 8-bit readable/writable up-counter. when tcwd overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrwd is set to 1. tcwd is initialized to h'00. 12.2.3 timer mode register wd (tmwd) tmwd selects the input clock. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 1 1 1 1 r/w r/w r/w r/w clock select 3 to 0 select the clock to be input to tcwd. 1000: internal clock: counts on f /64 1001: internal clock: counts on f /128 1010: internal clock: counts on f /256 1011: internal clock: counts on f /512 1100: internal clock: counts on f /1024 1101: internal clock: counts on f /2048 1110: internal clock: counts on f /4096 1111: internal clock: counts on f 8192 0xxx: internal oscillator for the internal oscillator overflow periods, see section 17, electrical characteristics. legend x: don't care. rev. 2.0, 03/02, page 154 of 298 12.3 operation the watchdog timer is provided with an 8-bit counter. if 1 is written to wdon while writing 0 to b2wi when the tcsrwe bit in tcsrwd is set to 1, tcwd begins counting up. (to operate the watchdog timer, two write accesses to tcsrwd are required.) when a clock pulse is input after the tcwd count value has reached h'ff, the watchdog timer overflows and an internal reset signal is generated. the internal reset signal is output for a period of 512 f osc clock cycles. tcwd is a writable counter, and when a value is set in tcwd, the count-up starts from that value. an overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the tcwd set value. figure 12.2 shows an example of watchdog timer operation. example: with 30ms overflow period when f = 4 mhz 4 10 6 30 10 C3 = 14.6 8192 tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated start 512 f osc clock cycles therefore, 256 C 15 = 241 (h'f1) is set in tcw. figure 12.2 watchdog timer operation example rev. 2.0, 03/02, page 155 of 298 section 13 serial communication interface3 (sci3) serial communication interface 3 (sci3) can handle both asynchronous and clocked synchronous serial communication. in the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function). figure 13.1 shows a block diagram of the sci3. 13.1 features choice of asynchronous or clocked synchronous serial communication mode full-duplex communication capability the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. on-chip baud rate generator allows any bit rate to be selected external clock or on-chip baud rate generator can be selected as a transfer clock source. six interrupt sources transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. asynchronous mode data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even, odd, or none receive error detection: parity, overrun, and framing errors break detection: break can be detected by reading the rxd pin level directly in the case of a framing error clocked synchronous mode data length: 8 bits receive error detection: overrun errors detected sci0010a_000020020300 rev. 2.0, 03/02, page 156 of 298 clock txd rxd sck 3 brr smr scr3 ssr tdr rdr tsr rsr transmit/receive control circuit internal data bus legend : rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter interrupt request (tei, txi, rxi, eri) internal clock (?/64, ?/16, ?/4, ?) external clock brc baud rate generator figure 13.1 block diagram of sci3 rev. 2.0, 03/02, page 157 of 298 13.2 input/output pins table 13.1 shows the sci3 pin configuration. table 13.1 pin configuration pin name abbreviation i/o function sci3 clock sck3 i/o sci3 clock input/output sci3 receive data input rxd input sci3 receive data input sci3 transmit data output txd output sci3 transmit data output 13.3 register descriptions the sci3 has the following registers. receive shift register (rsr) receive data register (rdr) transmit shift register (tsr) transmit data register (tdr) serial mode register (smr) serial control register 3 (scr3) serial status register (ssr) bit rate register (brr) rev. 2.0, 03/02, page 158 of 298 13.3.1 receive shift register (rsr) rsr is a shift register that is used to receive serial data input from the rxd pin and convert it into parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 13.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data. when the sci3 has received one byte of serial data, it transfers the received serial data from rsr to rdr, where it is stored. after this, rsr is receive-enabled. as rsr and rdr function as a double buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00. 13.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data from tdr to tsr automatically, then sends the data that starts from the lsb to the txd pin . tsr cannot be directly accessed by the cpu. 13.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sci3 detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transmission of one-frame data, the sci3 transfers the written data to tsr to continue transmission. to achieve reliable serial transmission, write transmit data to tdr only once after confirming that the tdre bit in ssr is set to 1. tdr is initialized to h'ff. rev. 2.0, 03/02, page 159 of 298 13.3.5 serial mode register (smr) smr is used to set the sci3s serial transfer format and select the on-chip baud rate generator clock source. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. 5pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and pm bit settings are invalid. in clocked synchronous mode, this bit should be cleared to 0. rev. 2.0, 03/02, page 160 of 298 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the on-chip baud rate generator. 00: ? clock (n = 0) 01: ?/4 clock (n = 1) 10: ?/16 clock (n = 2) 11: ?/64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 13.3.8, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 13.3.8, bit rate register (brr)). 13.3.6 serial control register 3 ( scr3) scr3 is a register that enables or disables sci3 transfer operations and interrupt requests, and is also used to select the transfer clock source. for details on interrupt requests, refer to section 13.7, interrupts. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. rev. 2.0, 03/02, page 161 of 298 bit bit name initial value r/w description 3mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and oer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 13.6, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, the tei interrupt request is enabled. 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source. asynchronous mode: 00: internal baud rate generator 01: internal baud rate generator outputs a clock of the same frequency as the bit rate from the sck3 pin. 10: external clock inputs a clock with a frequency 16 times the bit rate from the sck3 pin. 11:reserved clocked synchronous mode: 00: internal clock (sck3 pin functions as clock output) 01:reserved 10: external clock (sck3 pin functions as clock input) 11:reserved rev. 2.0, 03/02, page 162 of 298 13.3.7 serial status register ( ssr) ssr is a register containing status flags of the sci3 and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty displays whether tdr contains transmit data. [setting conditions] when the te bit in scr3 is 0 when data is transferred from tdr to tsr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the transmit data is written to tdr 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when data is read from rdr 5 oer 0 r/w overrun error [setting condition] when an overrun error occurs in reception [clearing condition] when 0 is written to oer after reading oer = 1 rev. 2.0, 03/02, page 163 of 298 bit bit name initial value r/w description 4 fer 0 r/w framing error [setting condition] when a framing error occurs in reception [clearing condition] when 0 is written to fer after reading fer = 1 3 per 0 r/w parity error [setting condition] when a parity error is generated during reception [clearing condition] when 0 is written to per after reading per = 1 2 tend 1 r transmit end [setting conditions] when the te bit in scr3 is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing conditions] when 0 is written to tend after reading tend = 1 when the transmit data is written to tdr 1 mpbr 0 r multiprocessor bit receive mpbr stores the multiprocessor bit in the receive character data. when the re bit in scr3 is cleared to 0, its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit character data. rev. 2.0, 03/02, page 164 of 298 13.3.8 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. the initial value of brr is h'ff. table 13.2 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in asynchronous mode. table 13.3 shows the maximum bit rate for each frequency in asynchronous mode. the values shown in both tables 13.2 and 13.3 are values in active (high- speed) mode. table 13.4 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 in smr in clocked synchronous mode. the values shown in table 13.4 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode] n = f 64 2 2nC1 b 10 6 C 1 error (%) = C 1 100 ? ? f 10 6 (n + 1) b 64 2 2nC1 [clocked synchronous mode] n = f 8 2 2nC1 b 10 6 C 1 note: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) f : operating frequency (mhz) n: cks1 and cks0 setting for smr (0 n 3) rev. 2.0, 03/02, page 165 of 298 table 13.2 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency ? (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 C0.04 1 174 C0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 C0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 C2.48 0 15 0.00 0 19 C2.34 9600 0 6 C6.99 0 6 C2.48 0 7 0.00 0 9 C2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 C2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 C18.62 0 1 C14.67 0 1 0.00 legend ? : a setting is available but error occurs operating frequency ? (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 C0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 C6.99 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 C1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 rev. 2.0, 03/02, page 166 of 298 table 13.2 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency ? (mhz) 6 6.144 7.3728 8 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 C0.44 2 108 0.08 2 130 C0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 C2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 C2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 C2.34 0 4 0.00 0 5 0.00 0 6 -6.99 operating frequency ? (mhz) 9.8304 10 12 12.888 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 C0.26 2 177 C0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 C1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 C2.34 0 19 0.00 31250 0 9 C1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 C2.34 0 9 0.00 rev. 2.0, 03/02, page 167 of 298 table 13.2 examples of brr settings for various bit rates (asynchronous mode) (3) operating frequency ? (mhz) 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 248 C0.17 3 64 0.70 3 70 0.03 150 2 181 0.16 2 191 0.00 2 207 0.16 300 2 90 0.16 2 95 0.00 2 103 0.16 600 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 45 C0.93 0 47 0.00 0 51 0.16 19200 0 22 C0.93 0 23 0.00 0 25 0.16 31250 0 13 0.00 0 14 C1.70 0 15 0.00 38400 0 11 0.00 0 12 0.16 legend : a setting is available but error occurs. table 13.3 maximum bit rate for each frequency (asynchronous mode) ? (mhz) maximum bit rate (bit/s) n n ? (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 7.3728 230400 0 0 2.097152 65536 0 0 8 250000 0 0 2.4576 76800 0 0 9.8304 307200 0 0 3 93750 0 0 10 312500 0 0 3.6864 115200 0 0 12 375000 0 0 4 125000 0 0 12.288 384000 0 0 4.9152 153600 0 0 14 437500 0 0 5 156250 0 0 14.7456 460800 0 0 6 187500 0 0 16 500000 0 0 6.144 192000 0 0 rev. 2.0, 03/02, page 168 of 298 table 13.4 brr settings for various bit rates (clocked synchronous mode) operating frequency ? (mhz) 2 4 8 10 16 bit rate (bit/s) nn nn nn nn nn 110 370 250 2 124 2 249 3 124 3 249 500 1 249 2 124 2 249 3 124 1k 1 124 1 249 2 124 2 249 2.5k 0 199 1 99 1 199 1 249 2 99 5k 0 99 0 199 1 99 1 124 1 199 10k 0 49 0 99 0 199 0 249 1 99 25k 0 19 0 39 0 79 0 99 0 159 50k 0 9 0 19 0 39 0 49 0 79 100k 0 4 0 9 0 19 0 24 0 39 250k 0 1 0 3 0 7 0 9 0 15 500k 0 0 * 01 03 04 07 1m 0 0 * 01 03 2m 0 0 * 0 1 2.5m 0 0 * 4m 00 * legend blank : no setting is available. : a setting is available but error occurs. * : continuous transfer is not possible. rev. 2.0, 03/02, page 169 of 298 13.4 operation in asynchronous mode figure 13.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). inside the sci3, the transmitter and receiver are independent units, enabling full duplex. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 13.2 data format in asynchronous communication 13.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck3 pin can be selected as the sci3s serial clock source, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr3. when an external clock is input at the sck3 pin, the clock frequency should be 16 times the bit rate used. when the sci3 is operated on an internal clock, the clock can be output from the sck3 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 13.3 relationship between output clock and transfer data phase (asynchronous mode)(example with 8-bit data, parity, two stop bits) rev. 2.0, 03/02, page 170 of 298 13.4.2 sci3 initialization follow the flowchart as shown in figure 13.4 to initialize the sci3. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait rev. 2.0, 03/02, page 171 of 298 13.4.3 data transmission figure 13.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if the flag is cleared to 0, the sci3 recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a txi interrupt request is generated. continuous transmission is possible because the txi interrupt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered, in which 1 is output. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 6. figure 13.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi interrupt request generated tei interrupt request generated figure 13.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit) rev. 2.0, 03/02, page 172 of 298 no rev. 2.0, 03/02, page 173 of 298 13.4.4 serial data reception figure 13.7 shows an example of operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives data in rsr, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi interrupt routine reads the receive data transferred to rdr before reception of the next receive data has been completed. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1 d0 d1 d7 0/1 1 0 1 0 d0 d1 d7 0/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 stop bit detected eri request in response to framing error figure 13.7 example sci3 operation in reception in asynchronous mode (8-bit data, parity, one stop bit) rev. 2.0, 03/02, page 174 of 298 table 13.5 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 13.8 shows a sample flowchart for serial data reception. table 13.5 ssr status flags and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1111lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had before data reception. rev. 2.0, 03/02, page 175 of 298 yes rev. 2.0, 03/02, page 176 of 298 rev. 2.0, 03/02, page 177 of 298 13.5 operation in clocked synchronous mode figure 13.9 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data consists of the 8-bit data starting from the lsb. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sci3 receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. both the transmitter and the receiver also have a double- buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. dont care dont care one unit of transfer data (character or frame) 8-bit bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 13.9 data format in clocked synchronous communication 13.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck3 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr3. when the sci3 is operated on an internal clock, the serial clock is output from the sck3 pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 13.5.2 sci3 initialization before transmitting and receiving data, the sci3 should be initialized as described in a sample flowchart in figure 13.4. rev. 2.0, 03/02, page 178 of 298 13.5.3 serial data transmission figure 13.10 shows an example of sci3 operation for transmission in clocked synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit in scr3 is set to 1 at this time, a transmit data empty interrupt (txi) is generated. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd pin. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 7. the sck3 pin is fixed high. figure 13.11 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi interrupt request generated data written to tdr tdre flag cleared to 0 txi interrupt request generated tei interrupt request generated figure 13.10 example of sci3 operation in transmission in clocked synchronous mode rev. 2.0, 03/02, page 179 of 298 no rev. 2.0, 03/02, page 180 of 298 13.5.4 serial data reception (clocked synchronous mode) figure 13.12 shows an example of sci3 operation for reception in clocked synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. the sci3 stores the received data in rsr. 3. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated, receive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is completed successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. serial clock serial data 1 frame 1 frame bit 0 bit 7 bit 7 bit 0 bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi interrupt request generated rdr data read rdrf flag cleared to 0 rxi interrupt request generated eri interrupt request generated by overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 13.12 example of sci3 reception operation in clocked synchronous mode reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 13.13 shows a sample flowchart for serial data reception. rev. 2.0, 03/02, page 181 of 298 yes rev. 2.0, 03/02, page 182 of 298 13.5.5 simultaneous serial data transmission and reception figure 13.14 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode, after checking that the sci3 has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously set te and re to 1 with a single instruction. rev. 2.0, 03/02, page 183 of 298 yes rev. 2.0, 03/02, page 184 of 298 13.6 multiprocessor communication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communication is performed, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles; an id transmission cycle that specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 13.15 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose ids do not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci3 uses the mpie bit in scr3 to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer to 1, are inhibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. rev. 2.0, 03/02, page 185 of 298 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend mpb: multiprocessor bit figure 13.15 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) rev. 2.0, 03/02, page 186 of 298 13.6.1 multiprocessor serial data transmission figure 13.16 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt bit in ssr to 0 before transmission. all other sci3 operations are the same as those in asynchronous mode. no rev. 2.0, 03/02, page 187 of 298 13.6.2 multiprocessor serial data reception figure 13.17 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. on receiving data with a 1 multiprocessor bit, the receive data is transferred to rdr. an rxi interrupt request is generated at this time. all other sci3 operations are the same as in asynchronous mode. figure 13.18 shows an example of sci3 operation for multiprocessor format reception. rev. 2.0, 03/02, page 188 of 298 yes rev. 2.0, 03/02, page 189 of 298 rev. 2.0, 03/02, page 190 of 298 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request is not generated, and rdr retains its state rdr data read when data is not this station's id, mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request rdrf flag cleared to 0 rdr data read when data is this station's id, reception is continued rdr data read mpie set to 1 again figure 13.18 example of sci3 operation in reception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit) rev. 2.0, 03/02, page 191 of 298 13.7 interrupts the sci3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). table 13.6 shows the interrupt sources. table 13.6 sci3 interrupt requests interrupt requests abbreviation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr3 is set to 1 before transferring the transmit data to tdr, a txi interrupt request is generated even if the transmit data is not ready. the initial value of the tend flag in ssr is 1. thus, when the teie bit in scr3 is set to 1 before transferring the transmit data to tdr, a tei interrupt request is generated even if the transmit data has not been sent. it is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi and tei), set the enable bits (tie and teie) that correspond to these interrupt requests to 1, after transferring the transmit data to tdr. 13.8 usage notes 13.8.1 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0, setting the fer flag, and possibly the per flag. note that as the sci3 continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 13.8.2 mark state and break sending when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by pcr and pdr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. rev. 2.0, 03/02, page 192 of 298 13.8.3 receive error flags and transmit operations (clocked synchronous mode only) transmission cannot be started when a receive error flag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. rev. 2.0, 03/02, page 193 of 298 13.8.4 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 13.19. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 C ) C C (l C 0.5) f 100(%) ? ? 1 2n d C 0.5 n ... formula (1) where n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0.5 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 C 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 13.19 receive data sampling timing in asynchronous mode rev. 2.0, 03/02, page 194 of 298 rev. 2.0, 03/02, page 195 of 298 section 14 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to four analog input channels to be selected. the block diagram of the a/d converter is shown in figure 14.1. 14.1 features 10-bit resolution four input channels conversion time: at least 4.4 m s per channel (at 16 mhz operation) two operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels four data registers ? conversion results are held in a 16-bit data register for each channel sample and hold function two conversion start methods ? software ? external trigger signal interrupt request ? an a/d conversion end interrupt request (adi) can be generated adcms31a_000020020300 rev. 2.0, 03/02, page 196 of 298 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt request bus interface successive approximations register analog multiplexer a d c s r a d c r a d d r d a d d r c a d d r b a d d r a an0 an1 an2 an3 legend adcr : a/d control register adcsr : a/d control/status register addra : a/d data register a addrb : a/d data register b addrc : a/d data register c addrd : a/d data register d ?/4 ?/8 av cc figure 14.1 block diagram of a/d converter rev. 2.0, 03/02, page 197 of 298 14.2 input/output pins table 14.1 summarizes the input pins used by the a/d converter. table 14.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply pin analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pins a/d external trigger input pin $'75* input external trigger input pin for starting a/d conversion rev. 2.0, 03/02, page 198 of 298 14.3 register description the a/d converter has the following registers. a/d data register a (addra) a/d data register b (addrb) a/d data register c (addrc) a/d data register d (addrd) a/d control/status register (adcsr) a/d control register (adcr) 14.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which store a conversion result for each channel, are shown in table 14.2. the converted 10-bit data is stored in bits 6 to 15. the lower 6 bits are always read as 0. the data bus between the cpu and the a/d converter is 8 bits wide. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. the temporary register contents are transferred from the addr when the upper byte data is read. when reading addr, read the upper bytes only or read in word units. addr is initialized to h'0000. table 14.2 analog input channels and corresponding addr registers analog input channel a/d data register to be stored results of a/d conversion an0 addra an1 addrb an2 addrc an3 addrd rev. 2.0, 03/02, page 199 of 298 14.3.2 a/d control/status register (adcsr) adcsr consists of the control bits and conversion end status bits of the a/d converter. bit bit name initial value r/w description 7 adf 0 r/w a/d end flag [setting conditions] when a/d conversion ends in single mode when a/d conversion ends on all the channels selected in scan mode [clearing conditions] when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt (adi) request enabled by adf when 1 is set 5 adst 0 r/w a/d start setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode 3 cks 0 r/w clock select selects the a/d conversions time 0: conversion time = 134 states (max.) 1: conversion time = 70 states (max.) clear the adst bit to 0 before switching the conversion time. rev. 2.0, 03/02, page 200 of 298 bit bit name initial value r/w description 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 0 to 2 select analog input channels. when scan = 0 when scan = 1 000: an0 000: an0 001: an1 001: an0 to an1 010: an2 010: an0 to an2 011: an3 011: an0 to an3 14.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 trge 0 r/w trigger enable a/d conversion is started at the falling edge and the rising edge of the external trigger signal ( $'75* ) when this bit is set to 1. the selection between the falling edge and rising edge of the external trigger pin ( $'75* ) conforms to the wpeg5 bit in the interrupt edge select register 2 (iegr2) 6 to 1 all 1 reserved these bits are always read as 1. 0 0 r/wreserved do not set this bit to 1, though the bit is readable/writable. rev. 2.0, 03/02, page 201 of 298 14.4 operation the a/d converter operates by successive approximation with 10-bit resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit adst to 0 in adcsr. the adst bit can be set at the same time as the operating mode or analog input channel is changed. 14.4.1 single mode in single mode, a/d conversion is performed once for the analog input on the specified single channel as follows: 1. a/d conversion is started from the first channel when the adst bit in adcsr is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the result is transferred to the corresponding a/d data register to the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 14.4.2 scan mode in scan mode, a/d conversion is performed sequentially for the analog input on the specified channels (four channels maximum) as follows: 1. when the adst bit is set to 1 by software, or external trigger input, a/d conversion starts on the first channel in the group. 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt is requested. conversion of the first channel in the group starts again. 4. the adst bit is not automatically cleared to 0. steps [2] to [3] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. rev. 2.0, 03/02, page 202 of 298 14.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 14.2 shows the a/d conversion timing. table 14.3 shows the a/d conversion time. as indicated in figure 14.2, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 14.3. in scan mode, the values given in table 14.3 apply to the first conversion time. in the second and subsequent conversions, the conversion time is 128 states (fixed) when cks = 0 and 66 states (fixed) when cks = 1. (1) (2) t d t spl t conv ? address write signal input sampling timing adf legend (1) : adcsr write cycle (2) : adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 14.2 a/d conversion timing rev. 2.0, 03/02, page 203 of 298 table 14.3 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay t d 69 45 input sampling time t spl 31 15 a/d conversion time t conv 131 134 69 70 note: all values represent the number of states. 14.4.4 external trigger input timing a/d conversion can also be started by an external trigger input. when the trge bit is set to 1 in adcr, external trigger input is enabled at the $'75* pin. a falling edge at the $'75* input pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 14.3 shows the timing. ? internal trigger signal adst a/d conversion figure 14.3 external trigger input timing rev. 2.0, 03/02, page 204 of 298 14.5 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. resolution the number of a/d converter digital output codes quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 14.4). offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 14.5). full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 14.5). nonlinearity error the error with respect to the ideal a/d conversion characteristics between zero voltage and full-scale voltage. does not include offset error, full-scale error, or quantization error. absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization error, and nonlinearity error. 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 14.4 a/d conversion accuracy definitions (1) rev. 2.0, 03/02, page 205 of 298 fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 14.5 a/d conversion accuracy definitions (2) 14.6 usage notes 14.6.1 permissible signal source impedance this lsi's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k w or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k w , charging may be insufficient and it may not be possible to guarantee a/d conversion accuracy. however, for a/d conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k w , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ m s or greater) (see figure 14.6). when converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 14.6.2 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. rev. 2.0, 03/02, page 206 of 298 20 pf 10 k c in = 15 pf sensor output impedance to 5 k this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 14.6 analog input circuit example rev. 2.0, 03/02, page 207 of 298 section 15 power supply circuit this lsi incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approximately 3.0 v. if the external power supply is 3.0 v or below, the internal voltage will be practically the same as the external voltage. it is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit. 15.1 when using internal power supply step-down circuit connect the external power supply to the v cc pin, and connect a capacitance of approximately 0.1 f between v cl and v ss , as shown in figure 15.1. the internal step-down circuit is made effective simply by adding this external circuit. in the external circuit interface, the external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. the a/d converter analog power supply is not affected by the internal step-down circuit. v cl v ss internal logic step-down circuit internal power supply stabilization capacitance (approx. 0.1 m f) v cc v cc = 3.0 to 5.5 v figure 15.1 power supply connection when internal step-down circuit is used psckt00a_000020020300 rev. 2.0, 03/02, page 208 of 298 15.2 when not using internal power supply step-down circuit when the internal power supply step-down circuit is not used, connect the external power supply to the v cl pin and v cc pin, as shown in figure 15.2. the external power supply is then input directly to the internal power supply. the permissible range for the power supply voltage is 3.0 v to 3.6 v. operation cannot be guaranteed if a voltage outside this range (less than 3.0 v or more than 3.6 v) is input. v cl v ss internal logic step-down circuit internal power supply v cc v cc = 3.0 to 3.6 v figure 15.2 power supply connection when internal step-down circuit is not used rev. 2.0, 03/02, page 209 of 298 section 16 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) registers are listed from the lower allocation addresses. registers are classified by functional modules. the data bus width is indicated. the number of access states is indicated. 2. register bits bit configurations of the registers are described in the same order as the register addresses. reserved bits are indicated by ? in the bit name column. when registers consist of 16 bits, bits are described from the msb side. 3. register states in each operating mode register states are described in the same order as the register addresses. the register states described here are for the basic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. lvi0000a_000020020300 rev. 2.0, 03/02, page 210 of 298 16.1 register addresses (address order) the data bus width indicates the numbers of bits by which the register is accessed. the number of access states indicates the number of states based on the specified reference clock. register name abbre- viation bit no address module name data bus width access state timer mode register w tmrw 8 h'ff80 timer w 8 2 timer control register w tcrw 8 h'ff81 timer w 8 2 timer interrupt enable register w tierw 8 h'ff82 timer w 8 2 timer status register w tsrw 8 h'ff83 timer w 8 2 timer i/o control register 0 tior0 8 h'ff84 timer w 8 2 timer i/o control register 1 tior1 8 h'ff85 timer w 8 2 timer counter tcnt 16 h'ff86 timer w 16 * 1 2 general register a gra 16 h'ff88 timer w 16 * 1 2 general register b grb 16 h'ff8a timer w 16 * 1 2 general register c grc 16 h'ff8c timer w 16 * 1 2 general register d grd 16 h'ff8e timer w 16 * 1 2 flash memory control register 1 flmcr1 8 h'ff90 rom 8 2 flash memory control register 2 flmcr2 8 h'ff91 rom 8 2 erase block register 1 ebr1 8 h'ff93 rom 8 2 flash memory enable register fenr 8 h'ff9b rom 8 2 timer control register v0 tcrv0 8 h'ffa0 timer v 8 3 timer control/status register v tcsrv 8 h'ffa1 timer v 8 3 timer constant register a tcora 8 h'ffa2 timer v 8 3 timer constant register b tcorb 8 h'ffa3 timer v 8 3 timer counter v tcntv 8 h'ffa4 timer v 8 3 timer control register v1 tcrv1 8 h'ffa5 timer v 8 3 serial mode register smr 8 h'ffa8 sci3 8 3 bit rate register brr 8 h'ffa9 sci3 8 3 serial control register 3 scr3 8 h'ffaa sci3 8 3 rev. 2.0, 03/02, page 211 of 298 register name abbre- viation bit no address module name data bus width access state transmit data register tdr 8 h'ffab sci3 8 3 serial status register ssr 8 h'ffac sci3 8 3 receive data register rdr 8 h'ffad sci3 8 3 a/d data register a addra 16 h'ffb0 a/d converter 8 3 a/d data register b addrb 16 h'ffb2 a/d converter 8 3 a/d data register c addrc 16 h'ffb4 a/d converter 8 3 a/d data register d addrd 16 h'ffb6 a/d converter 8 3 a/d control/status register adcsr 8 h'ffb8 a/d converter 8 3 a/d control register adcr 8 h'ffb9 a/d converter 8 3 timer control/status register wd tcsrwd 8 h'ffc0 wdt * 2 82 timer counter wd tcwd 8 h'ffc1 wdt * 2 82 timer mode register wd tmwd 8 h'ffc2 wdt * 2 82 address break control register abrkcr 8 h'ffc8 address break 8 2 address break status register abrksr 8 h'ffc9 address break 8 2 break address register h barh 8 h'ffca address break 8 2 break address register l barl 8 h'ffcb address break 8 2 break data register h bdrh 8 h'ffcc address break 8 2 break data register l bdrl 8 h'ffcd address break 8 2 port pull-up control register 1 pucr1 8 h'ffd0 i/o port 8 2 port pull-up control register 5 pucr5 8 h'ffd1 i/o port 8 2 port data register 1 pdr1 8 h'ffd4 i/o port 8 2 port data register 2 pdr2 8 h'ffd5 i/o port 8 2 port data register 5 pdr5 8 h'ffd8 i/o port 8 2 port data register 7 pdr7 8 h'ffda i/o port 8 2 port data register 8 pdr8 8 h'ffdb i/o port 8 2 rev. 2.0, 03/02, page 212 of 298 register name abbre- viation bit no address module name data bus width access state port data register b pdrb 8 h'ffdd i/o port 8 2 port mode register 1 pmr1 8 h'ffe0 i/o port 8 2 port mode register 5 pmr5 8 h'ffe1 i/o port 8 2 port control register 1 pcr1 8 h'ffe4 i/o port 8 2 port control register 2 pcr2 8 h'ffe5 i/o port 8 2 port control register 5 pcr5 8 h'ffe8 i/o port 8 2 port control register 7 pcr7 8 h'ffea i/o port 8 2 port control register 8 pcr8 8 h'ffeb i/o port 8 2 system control register 1 syscr1 8 h'fff0 power-down 8 2 system control register 2 syscr2 8 h'fff1 power-down 8 2 interrupt edge select register 1 iegr1 8 h'fff2 interrupts 8 2 interrupt edge select register 2 iegr2 8 h'fff3 interrupts 8 2 interrupt enable register 1 ienr1 8 h'fff4 interrupts 8 2 interrupt flag register 1 irr1 8 h'fff6 interrupts 8 2 wake-up interrupt flag register iwpr 8 h'fff8 interrupts 8 2 module standby control register 1 mstcr1 8 h'fff9 power-down 8 2 notes: 1. only word access can be used. 2. wdt: watchdog timer rev. 2.0, 03/02, page 213 of 298 16.2 register bits register bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit registers are shown as 2 lines. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name tmrw cts bufeb bufea pwmd pwmc pwmb timer w tcrw cclr cks2 cks1 cks0 tod toc tob toa tierw ovie imied imiec imieb imiea tsrw ovf imfd imfc imfb imfa tior0 iob2 iob1 iob0 ioa2 ioa1 ioa0 tior1 iod2 iod1 iod0 ioc2 ioc1 ioc0 tcnt tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 gra gra15 gra14 gra13 gra12 gra11 gra10 gra9 gra8 gra7 gra6 gra5 gra4 gra3 gra2 gra1 gra0 grb grb15 grb14 grb13 grb12 grb11 grb10 grb9 grb8 grb7 grb6 grb5 grb4 grb3 grb2 grb1 grb0 grc grc15 grc14 grc13 grc12 grc11 grc10 grc9 grc8 grc7 grc6 grc5 grc4 grc3 grc2 grc1 grc0 grd grd15 grd14 grd13 grd12 grd11 grd10 grd9 grd8 grd7 grd6 grd5 grd4 grd3 grd2 grd1 grd0 flmcr1 swe esu psu ev pv e p rom flmcr2fler ebr1 eb4 eb3 eb2 eb1 eb0 fenrflshe tcrv0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 timer v tcsrv cmfb cmfa ovf os3 os2 os1 os0 tcora tcora7 tcora6 tcora5 tcora4 tcora3 tcora2 tcora1 tcora0 tcorb tcorb7 tcorb6 tcorb5 tcorb4 tcorb3 tcorb2 tcorb1 tcorb0 tcntv tcntv7 tcntv6 tcntv5 tcntv4 tcntv3 tcntv2 tcntv1 tcntv0 tcrv1 tveg1 tveg0 trge icks0 smr com chr pe pm stop mp cks1 cks0 sci3 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 rev. 2.0, 03/02, page 214 of 298 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ssr tdre rdrf oer fer per tend mpbr mpbt sci3 rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 addra ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter ad1ad0 addrb ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1ad0 addrc ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1ad0 addrd ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1ad0 adcsr adf adie adst scan cks ch2 ch1 ch0 adcrtrge tcsrwd b6wi tcwe b4wi tcsrwe b2wi wdon b0wi wrst wdt * tcwd tcwd7 tcwd6 tcwd5 tcwd4 tcwd3 tcwd2 tcwd1 tcwd0 tmwd cks3 cks2 cks1 cks0 abrkcr rtinte csel1 csel0 acmp2 acmp1 acmp0 dcmp1 dcmp0 address break abrksr abif abie barh barh7 barh6 barh5 barh4 barh3 barh2 barh1 barh0 barl barl7 barl6 barl5 barl4 barl3 barl2 barl1 barl0 bdrh bdrh7 bdrh6 bdrh5 bdrh4 bdrh3 bdrh2 bdrh1 bdrh0 bdrl bdrl7 bdrl6 bdrl5 bdrl4 bdrl3 bdrl2 bdrl1 bdrl0 pucr1 pucr17 pucr16 pucr15 pucr14 pucr12 pucr11 pucr10 i/o port pucr5 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 pdr1 p17 p16 p15 p14 p12 p11 p10 pdr2 p22 p21 p20 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 pdr7p76p75p74 pdr8 p84 p83 p82 p81 p80 rev. 2.0, 03/02, page 215 of 298 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pdrb pb3 pb2 pb1 pb0 i/o port pmr1 irq3 irq0 txd pmr5 pof7 pof6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 pcr1 pcr17 pcr16 pcr15 pcr14 pcr12 pcr11 pcr10 pcr2 pcr22 pcr21 pcr20 pcr5 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 pcr7 pcr76 pcr75 pcr74 pcr8 pcr84 pcr83 pcr82 pcr81 pcr80 syscr1 ssby sts2 sts1 sts0 power-down syscr2 smsel dton ma2 ma1 ma0 iegr1 ieg3 ieg0 interrupts iegr2 wpeg5 wpeg4 wpeg3 wpeg2 wpeg1 wpeg0 ienr1 iendt ienwp ien3 ien0 irr1 irrdt irri3 irri0 iwpr iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 mstcr1 msts3 mstad mstwd msttw msttv power-down note: * wdt: watchdog timer rev. 2.0, 03/02, page 216 of 298 16.3 register states in each operating mode register name reset active sleep subsleep standby module tmrw initialized timer w tcrw initialized tierw initialized tsrw initialized tior0 initialized tior1 initialized tcnt initialized gra initialized grb initialized grc initialized grd initialized flmcr1 initialized initialized initialized rom flmcr2 initialized initialized initialized ebr1 initialized initialized initialized fenr initialized initialized initialized tcrv0 initialized initialized initialized timer v tcsrv initialized initialized initialized tcora initialized initialized initialized tcorb initialized initialized initialized tcntv initialized initialized initialized tcrv1 initialized initialized initialized smr initialized initialized initialized sci3 brr initialized initialized initialized scr3 initialized initialized initialized tdr initialized initialized initialized ssr initialized initialized initialized rdr initialized initialized initialized rev. 2.0, 03/02, page 217 of 298 register name reset active sleep subsleep standby module addra initialized initialized initialized a/d converter addrb initialized initialized initialized addrc initialized initialized initialized addrd initialized initialized initialized adcsr initialized initialized initialized adcr initialized initialized initialized tcsrwd initialized wdt * tcwd initialized tmwd initialized abrkcr initialized address break abrksr initialized barh initialized barl initialized bdrh initialized bdrl initialized pucr1 initialized i/o port pucr5 initialized pdr1 initialized pdr2 initialized pdr5 initialized pdr7 initialized pdr8 initialized pdrb initialized pmr1 initialized pmr5 initialized pcr1 initialized pcr2 initialized pcr5 initialized pcr7 initialized pcr8 initialized rev. 2.0, 03/02, page 218 of 298 register name reset active sleep supsleep standby module syscr1 initialized power-down syscr2 initialized iegr1 initialized interrupts iegr2 initialized ienr1 initialized irr1 initialized iwpr initialized mstcr1 initialized power-down notes: ? is not initialized * wdt: watchdog timer rev. 2.0, 03/02, page 219 of 298 section 17 electrical characteristics 17.1 absolute maximum ratings table 17.1 absolute maximum ratings item symbol value unit note power supply voltage v cc C0.3 to +7.0 v * analog power supply voltage av cc C0.3 to +7.0 v input voltage ports other than port b v in C0.3 to v cc +0.3 v port b C0.3 to av cc +0.3 v operating temperature t opr C20 to +75 c storage temperature t stg C55 to +125 c note: * permanent damage may result if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 17.2 electrical characteristics 17.2.1 power supply voltage and operating ranges power supply voltage and oscillation frequency range 10.0 2.0 16.0 3.0 4.0 5.5 v cc (v) ? osc (mhz) 32.768 3.0 4.0 5.5 v cc (v) ? w (khz) ? av cc = 3.3 v to 5.5 v ? active mode ? sleep mode ? av cc = 3.3 v to 5.5 v ? all operating modes rev. 2.0, 03/02, page 220 of 298 power supply voltage and operating frequency range 10.0 1.0 16.0 3.0 4.0 5.5 v cc (v) ? (mhz) 1250 78.125 2000 3.0 4.0 5.5 v cc (v) ? (khz) ? av cc = 3.3 v to 5.5 v ? active mode ? sleep mode (when ma2 = 0 in syscr2) ? av cc = 3.3 v to 5.5 v ? active mode ? sleep mode (when ma2 = 1 in syscr2) analog power supply voltage and a/d converter accuracy guarantee range 10.0 2.0 16.0 3.3 4.0 5.5 av cc (v) ? (mhz) ? v cc = 3.0 v to 5.5 v ? active mode ? sleep mode rev. 2.0, 03/02, page 221 of 298 17.2.2 dc characteristics table 17.2 dc characteristics (1) v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = C20c to +75c unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes input high voltage v ih 5(6 , :.3 to :.3 , ,54 to ,54 , $'75* ,tmriv, v cc = 4.0 v to 5.5 v v cc 0.8 v cc + 0.3 v tmciv, ftci, ftioa to ftiod, sck3, trgv v cc 0.9 v cc + 0.3 rxd, p12 to p10, p17 to p14, p22 to p20, v cc = 4.0 v to 5.5 v v cc 0.7 v cc + 0.3 v p57 to p50, p76 to p74, p84 to p80 v cc 0.8 v cc + 0.3 pb3 to pb0 v cc = 4.0 v to 5.5 v v cc 0.7 av cc + 0.3 v v cc 0.8 av cc + 0.3 osc 1 v cc = 4.0 v to 5.5 v v cc C 0.5 v cc + 0.3 v v cc C 0.3 v cc + 0.3 input low voltage v il 5(6 , :.3 to :.3 , ,54 , ,54 , $'75* ,tmriv, v cc = 4.0 v to 5.5 v C0.3 v cc 0.2 v tmciv, ftci, ftioa to ftiod, sck3, trgv C0.3 v cc 0.1 rxd, p12 to p10, p17 to p14, p22 to p20, v cc = 4.0 v to 5.5 v C0.3 v cc 0.3 v p57 to p50, p76 to p74, p84 to p80, pb3 to pb0 C0.3 v cc 0.2 osc1 v cc = 4.0 v to 5.5 v C0.3 0.5 v C0.3 0.3 rev. 2.0, 03/02, page 222 of 298 values item symbol applicable pins test condition min typ max unit notes output high voltage v oh v cc = 4.0 v to 5.5 v Ci oh = 1.5 ma v cc C 1.0 v p12 to p10, p17 to p14, p22 to p20, p57 to p50, p76 to p74, p84 to p80 Ci oh = 0.1 ma v cc C 0.5 output low voltage v ol v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.6 v p12 to p10, p17 to p14, p22 to p20, p55 to p50, p76 to p74 i ol = 0.4 ma 0.4 p84 to p80 v cc = 4.0 v to 5.5 v i ol = 20.0 ma 1.5 v v cc = 4.0 v to 5.5 v i ol = 10.0 ma 1.0 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.4 i ol = 0.4 ma 0.4 rev. 2.0, 03/02, page 223 of 298 values item symbol applicable pins test condition min typ max unit notes input/ output leakage current | i il | osc1, 5(6 , :.3 to :.3 , ,54 , ,54 , $'75* , trgv, tmriv, tmciv, ftci, ftioa to ftiod, rxd, sck3 v in = 0.5 v or higher (v cc C 0.5 v) 1.0a p12 to p10, p17 to p14, p22 to p20, p57 to p50, p76 to p74, p84 to p80 v in = 0.5 v or higher (v cc C 0.5 v) 1.0a pb3 to pb0 v in = 0.5 v or higher (av cc C 0.5 v) 1.0a pull-up mos Ci p p12 to p10, p17 to p14, v cc = 5.0 v, v in = 0.0 v 50.0 300.0 a current p55 to p50 v cc = 3.0 v, v in = 0.0 v 60.0 reference value input capaci- tance c in all input pins except power supply pins f = 1 mhz, v in = 0.0 v, t a = 25c 15.0 pf i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 16 mhz 15.0 22.5 ma * active mode current consump- tion active mode 1 v cc = 3.0 v, f osc = 10 mhz 8.0 * reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 16 mhz 1.82.7ma * active mode 2 v cc = 3.0 v, f osc = 10 mhz 1.2 * reference value rev. 2.0, 03/02, page 224 of 298 values item symbol applicable pins test condition min typ max unit notes i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 16 mhz 11.5 17.0 ma * sleep mode current consump- tion sleep mode 1 v cc = 3.0 v, f osc = 10 mhz 6.5 * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 16 mhz 1.72.5 ma * sleep mode 2 v cc = 3.0 v, f osc = 10 mhz 1.1 * reference value standby mode current consump- tion i stby v cc 32-khz crystal resonator not used 5.0 a * ram data retaining voltage v ram v cc 2.0 v note: * pin states during current consumption measurement are given below (excluding current in the pull-up mos transistors and output buffers). rev. 2.0, 03/02, page 225 of 298 mode 5(6 5(6 pin internal state other pins oscillator pins active mode 1 v cc operates v cc active mode 2 operates (?/64) main clock: ceramic or crystal resonator sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate (?/64) standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator table 17.2 dc characteristics (2) v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = C20c to +75c, unless otherwise indicated. applicable values item symbol pins test condition min typ max unit allowable output low current (per pin) i ol output pins except port 8 v cc = 4.0 v to 5.5 v 2.0ma port 8 20.0 ma port 8 10.0 ma output pins except port 8 0.5ma allowable output low current (total) ? i ol output pins except port 8 v cc = 4.0 v to 5.5 v 40.0 ma port 8 80.0 ma output pins except port 8 20.0 ma port 8 40.0 ma allowable output high ? Ci oh ? all output pins v cc = 4.0 v to 5.5 v 2.0ma current (per pin) 0.2ma allowable output high ? C ? Ci oh ? all output pins v cc = 4.0 v to 5.5 v 30.0 ma current (total) 8.0ma rev. 2.0, 03/02, page 226 of 298 17.2.3 ac characteristics table 17.3 ac characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. applicable values reference item symbol pins test condition min typ max unit figure system clock oscillation f osc osc1, osc2 v cc = 4.0 v to 5.5 v 2.0 16.0 mhz * 1 frequency 2.0 10.0 mhz system clock (?) t cyc 164t osc * 2 cycle time 12.8 s instruction cycle time 2 t cyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 5.0ms external clock t cph osc1 v cc = 4.0 v to 5.5 v 25.0 ns figure 17.1 high width 40.0 ns external clock t cpl osc1 v cc = 4.0 v to 5.5 v 25.0 ns low width 40.0 ns external clock t cpr osc1 v cc = 4.0 v to 5.5 v 10.0 ns rise time 15.0 ns external clock t cpf osc1 v cc = 4.0 v to 5.5 v 10.0 ns fall time 15.0 ns rev. 2.0, 03/02, page 227 of 298 applicable values reference item symbol pins test condition min typ max unit figure 5(6 pin low width t rel 5(6 at power-on and in modes other than those below t rc ms figure 17.2 in active mode and sleep mode operation 10t cyc input pin high width t ih ,54 , ,54 , :.3 to :.3 , tmciv, tmriv, trgv, $'75* , ftci, ftioa to ftiod 2 t cyc figure 17.3 input pin low width t il ,54 , ,54 , :.3 to :.3 , tmciv, tmriv, trgv, $'75* , ftci, ftioa to ftiod 2 t cyc notes: 1. when an external clock is input, the minimum system clock oscillator frequency is 1.0 mhz. 2. determined by ma2 to ma0 in system control register 2 (syscr2). rev. 2.0, 03/02, page 228 of 298 table 17.4 serial interface (sci3) timing v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. a pp licable values reference item symbol pins test condition min typ max unit figure input clock asynchro- nous t scyc sck3 4 t cyc figure 17.4 cycle clocked synchro- nous 6t cyc input clock pulse width t sckw sck3 0.4 0.6 t scyc transmit data delay t txd txd v cc = 4.0 v to 5.5 v 1 t cyc figure 17.5 time (clocked synchronous) 1t cyc receive data setup t rxs rxd v cc = 4.0 v to 5.5 v 62.5 ns time (clocked synchronous) 100.0 ns receive data hold t rxh rxd v cc = 4.0 v to 5.5 v 62.5 ns time (clocked synchronous) 100.0 ns rev. 2.0, 03/02, page 229 of 298 17.2.4 a/d converter characteristics table 17.5 a/d converter characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. applicable test values reference item symbol pins condition min typ max unit figure analog power supply voltage av cc av cc 3.3 v cc 5.5 v * 1 analog input voltage av in an3 to an0 v ss C 0.3 av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 16 mhz 2.0ma ai stop1 av cc 50a * 2 reference value ai stop2 av cc 5.0a * 3 analog input capacitance c ain an3 to an0 30.0 pf allowable signal source impedance r ain an3 to an0 5.0k w resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.3 v to 5.5 v 134 t cyc nonlinearity error 7.5 lsb offset error 7.5 lsb full-scale error 7.5 lsb quantization error 0.5 lsb absolute accuracy 8.0 lsb conversion time (single mode) av cc = 4.0 v to 5.5 v 70 t cyc nonlinearity error 7.5 lsb offset error 7.5 lsb full-scale error 7.5 lsb quantization error 0.5 lsb absolute accuracy 8.0 lsb rev. 2.0, 03/02, page 230 of 298 applicable test values reference item symbol pins condition min typ max unit figure conversion time (single mode) av cc = 4.0 v to 5.5 v 134 t cyc nonlinearity error 3.5 lsb offset error 3.5 lsb full-scale error 3.5 lsb quantization error 0.5 lsb absolute accuracy 4.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby and subsleep modes while the a/d converter is idle. 17.2.5 watchdog timer table 17.6 watchdog timer characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. applicable test values reference item symbol pins condition min typ max unit figure on-chip oscillator overflow time t ovf 0.2 0.4 s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected. rev. 2.0, 03/02, page 231 of 298 17.2.6 flash memory characteristics (preliminary) table 17.7 flash memory characteristics (preliminary) v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. test values item symbol condition min typ max unit programming time (per 128 bytes) * 1 * 2 * 4 t p 7 ms erase time (per block) * 1 * 3 * 6 t e 100ms reprogramming count n wec 1000 times programming wait time after swe bit setting * 1 x1s wait time after psu bit setting * 1 y50s wait time after p bit setting z1 1 n 6 283032s * 1 * 4 z2 7 n 1000 198 200 202 s z3 additional- programming 81012s wait time after p bit clear * 1 a 5s wait time after psu bit clear * 1 b 5s wait time after pv bit setting * 1 g 4s wait time after dummy write * 1 e 2s wait time after pv bit clear * 1 h 2s wait time after swe bit clear * 1 q 100 s maximum programming count * 1 * 4 * 5 n 1000 times rev. 2.0, 03/02, page 232 of 298 test values item symbol condition min typ max unit erase wait time after swe bit setting * 1 x1s wait time after esu bit setting * 1 y100s wait time after e bit setting * 1 * 6 z10100ms wait time after e bit clear * 1 a 10 s wait time after esu bit clear * 1 b 10 s wait time after ev bit setting * 1 g 20 s wait time after dummy write * 1 e 2s wait time after ev bit clear * 1 h 4s wait time after swe bit clear * 1 q 100 s maximum erase count * 1 * 6 * 7 n120times notes: 1. make the time settings in accordance with the program/erase algorithms. 2. the programming time for 128 bytes. (indicates the total time for which the p bit in flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) 3. the time required to erase one block. (indicates the time for which the e bit in flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) 4. programming time maximum value (t p (max)) = wait time after p bit setting (z) maximum programming count (n) 5. set the maximum programming count (n) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (t p (max)). the wait time after p bit setting (z1, z2) should be changed as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. erase time maximum value (t e (max)) = wait time after e bit setting (z) maximum erase count (n) 7. set the maximum maximum erase count (n) according to the actual set value of (z), so that it does not exceed the erase time maximum value (t e (max)). rev. 2.0, 03/02, page 233 of 298 17.3 operation timing t osc v ih v il t cph t cpl t cpr osc1 t cpf figure 17.1 system clock input timing t rel v il t rel v il v cc 0.7 v cc osc1 figure 17.2 5(6 5(6 low width timing v ih v il t il , to ftci ftioa to ftiod tmciv, tmriv trgv t ih figure 17.3 input timing rev. 2.0, 03/02, page 234 of 298 t scyc t sckw sck3 figure 17.4 sck3 input clock timing t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol * sck3 txd (transmit data) rxd (receive data) note: * output timing reference levels output high: output low: load conditions are shown in figure 16.6. v = 2.0 v v = 0.8 v oh ol figure 17.5 sci3 input/output timing in clocked synchronous mode rev. 2.0, 03/02, page 235 of 298 17.4 output load condition v cc 2.4 k w 12 k w 30 pf lsi output pin figure 17.6 output load circuit rev. 2.0, 03/02, page 236 of 298 rev. 2.0, 03/02, page 237 of 298 appendix a instruction set a.1 instruction list operand notation symbol description rd general (destination * ) register rs general (source * ) register rn general register * erd general destination register (address register or 32-bit register) ers general source register (address register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement ? transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides C subtraction of the operand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides ? logical exclusive or of the operands on both sides ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7). rev. 2.0, 03/02, page 238 of 298 condition code notation symbol description ? changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 not affected by execution of the instruction d varies depending on conditions, described in notes rev. 2.0, 03/02, page 239 of 298 table a.1 instruction set 1. data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @Cerd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) operation #xx:8 ? rd8 rs8 ? rd8 @ers ? rd8 @(d:16, ers) ? rd8 @(d:24, ers) ? rd8 @ers ? rd8 ers32+1 ? ers32 @aa:8 ? rd8 @aa:16 ? rd8 @aa:24 ? rd8 rs8 ? @erd rs8 ? @(d:16, erd) rs8 ? @(d:24, erd) erd32C1 ? erd32 rs8 ? @erd rs8 ? @aa:8 rs8 ? @aa:16 rs8 ? @aa:24 #xx:16 ? rd16 rs16 ? rd16 @ers ? rd16 @(d:16, ers) ? rd16 @(d:24, ers) ? rd16 @ers ? rd16 ers32+2 ? @erd32 @aa:16 ? rd16 @aa:24 ? rd16 rs16 ? @erd rs16 ? @(d:16, erd) rs16 ? @(d:24, erd) b b b b b b b b b b b b b b b b w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 4 6 2 4 6 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov rev. 2.0, 03/02, page 240 of 298 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa mov.w rs, @Cerd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @Cerd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 operation erd32C2 ? erd32 rs16 ? @erd rs16 ? @aa:16 rs16 ? @aa:24 #xx:32 ? rd32 ers32 ? erd32 @ers ? erd32 @(d:16, ers) ? erd32 @(d:24, ers) ? erd32 @ers ? erd32 ers32+4 ? ers32 @aa:16 ? erd32 @aa:24 ? erd32 ers32 ? @erd ers32 ? @(d:16, erd) ers32 ? @(d:24, erd) erd32C4 ? erd32 ers32 ? @erd ers32 ? @aa:16 ers32 ? @aa:24 @sp ? rn16 sp+2 ? sp @sp ? ern32 sp+4 ? sp spC2 ? sp rn16 ? @sp spC4 ? sp ern32 ? @sp cannot be used in this lsi cannot be used in this lsi w w w l l l l l l l l l l l l l l w l w l b b 6 2 4 4 6 10 6 10 2 4 4 4 6 6 8 6 8 4 4 2 4 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi cannot be used in this lsi mov pop push movfpe movtpe rev. 2.0, 03/02, page 241 of 298 2. arithmetic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd operation rd8+#xx:8 ? rd8 rd8+rs8 ? rd8 rd16+#xx:16 ? rd16 rd16+rs16 ? rd16 erd32+#xx:32 ? erd32 erd32+ers32 ? erd32 rd8+#xx:8 +c ? rd8 rd8+rs8 +c ? rd8 erd32+1 ? erd32 erd32+2 ? erd32 erd32+4 ? erd32 rd8+1 ? rd8 rd16+1 ? rd16 rd16+2 ? rd16 erd32+1 ? erd32 erd32+2 ? erd32 rd8 decimal adjust ? rd8 rd8Crs8 ? rd8 rd16C#xx:16 ? rd16 rd16Crs16 ? rd16 erd32C#xx:32 ? erd32 erd32Cers32 ? erd32 rd8C#xx:8Cc ? rd8 rd8Crs8Cc ? rd8 erd32C1 ? erd32 erd32C2 ? erd32 erd32C4 ? erd32 rd8C1 ? rd8 rd16C1 ? rd16 rd16C2 ? rd16 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (1) (1) (2) (2) * (1) (1) (2) (2) 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) (3) (3) (3) ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? add addx adds inc daa sub subx subs dec rev. 2.0, 03/02, page 242 of 298 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd operation erd32C1 ? erd32 erd32C2 ? erd32 rd8 decimal adjust ? rd8 rd8 rs8 ? rd16 (unsigned multiplication) rd16 rs16 ? erd32 (unsigned multiplication) rd8 rs8 ? rd16 (signed multiplication) rd16 rs16 ? erd32 (signed multiplication) rd16 ? rs8 ? rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 ? rs16 ? erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 ? rs8 ? rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 ? rs16 ? erd32 (ed: remainder, rd: quotient) (signed division) rd8C#xx:8 rd8Crs8 rd16C#xx:16 rd16Crs16 erd32C#xx:32 erd32Cers32 l l b b w b w b w b w b b w w l l 2 4 6 2 2 2 2 2 4 4 2 2 4 4 2 2 2 2 2 2 14 22 16 24 14 22 16 24 2 2 4 2 4 2 normal advanced ? ? ? * (1) (1) (2) (2) ? ? ? ? ? * (7) (7) (7) (7) (6) (6) (8) (8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dec das mulxu mulxs divxu divxs cmp rev. 2.0, 03/02, page 243 of 298 mnemonic operation operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd 0Crd8 ? rd8 0Crd16 ? rd16 0Cerd32 ? erd32 0 ? ( rev. 2.0, 03/02, page 244 of 298 3. logic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd operation rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd16 #xx:16 ? rd16 rd16 rs16 ? rd16 erd32 #xx:32 ? erd32 erd32 ers32 ? erd32 rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd16 #xx:16 ? rd16 rd16 rs16 ? rd16 erd32 #xx:32 ? erd32 erd32 ers32 ? erd32 rd8 ? #xx:8 ? rd8 rd8 ? rs8 ? rd8 rd16 ? #xx:16 ? rd16 rd16 ? rs16 ? rd16 erd32 ? #xx:32 ? erd32 erd32 ? ers32 ? erd32 ? rd8 ? rd8 ? rd16 ? rd16 ? rd32 ? rd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and or xor not rev. 2.0, 03/02, page 245 of 298 4. shift instructions mnemonic operand size no. of states * 1 condition code ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 operation msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? shal shar shll shlr rotxl rotxr rotl rotr rev. 2.0, 03/02, page 246 of 298 5. bit manipulation instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd operation (#xx:3 of rd8) ? 1 (#xx:3 of @erd) ? 1 (#xx:3 of @aa:8) ? 1 (rn8 of rd8) ? 1 (rn8 of @erd) ? 1 (rn8 of @aa:8) ? 1 (#xx:3 of rd8) ? 0 (#xx:3 of @erd) ? 0 (#xx:3 of @aa:8) ? 0 (rn8 of rd8) ? 0 (rn8 of @erd) ? 0 (rn8 of @aa:8) ? 0 (#xx:3 of rd8) ? ? (#xx:3 of rd8) (#xx:3 of @erd) ? ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? ? (#xx:3 of @aa:8) (rn8 of rd8) ? ? (rn8 of rd8) (rn8 of @erd) ? ? (rn8 of @erd) (rn8 of @aa:8) ? ? (rn8 of @aa:8) ? (#xx:3 of rd8) ? z ? (#xx:3 of @erd) ? z ? (#xx:3 of @aa:8) ? z ? (rn8 of @rd8) ? z ? (rn8 of @erd) ? z ? (rn8 of @aa:8) ? z (#xx:3 of rd8) ? c b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 normal advanced ? ? ? ? ? ? ? bset bclr bnot btst bld rev. 2.0, 03/02, page 247 of 298 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 operation (#xx:3 of @erd) ? c (#xx:3 of @aa:8) ? c ? (#xx:3 of rd8) ? c ? (#xx:3 of @erd) ? c ? (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) c ? (#xx:3 of @erd24) c ? (#xx:3 of @aa:8) ? c ? (#xx:3 of rd8) ? c ? (#xx:3 of @erd24) ? c ? (#xx:3 of @aa:8) c (#xx:3 of rd8) ? c c (#xx:3 of @erd24) ? c c (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) ? c c ? (#xx:3 of @erd24) ? c c ? (#xx:3 of @aa:8) ? c c (#xx:3 of rd8) ? c c (#xx:3 of @erd24) ? c c (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) ? c c ? (#xx:3 of @erd24) ? c c ? (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) ? c c ? (#xx:3 of @erd24) ? c c ? (#xx:3 of @aa:8) ? c c ? ? (#xx:3 of rd8) ? c c ? ? (#xx:3 of @erd24) ? c c ? ? (#xx:3 of @aa:8) ? c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bld bild bst bist band biand bor bior bxor bixor rev. 2.0, 03/02, page 248 of 298 6. branching instructions mnemonic operand size no. of states * 1 condition code ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 normal advanced addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 operation always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n ? v = 0 n ? v = 1 z (n ? v) = 0 z (n ? v) = 1 if condition is true then pc ? pc+d else next; branch condition bcc rev. 2.0, 03/02, page 249 of 298 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts operation pc ? ern pc ? aa:24 pc ? @aa:8 pc ? @Csp pc ? pc+d:8 pc ? @Csp pc ? pc+d:16 pc ? @Csp pc ? ern pc ? @Csp pc ? aa:24 pc ? @Csp pc ? @aa:8 pc ? @sp+ 2 2 4 4 2 4 2 2 2 4 6 normal advanced 8 6 8 6 8 8 8 10 8 10 8 10 12 10 jmp bsr jsr rts rev. 2.0, 03/02, page 250 of 298 7. system control instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @Cerd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop operation pc ? @Csp ccr ? @Csp rev. 2.0, 03/02, page 251 of 298 8. block transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @Cern/@ern+ @aa @(d, pc) @@aa eepmov. b eepmov. w operation if r4l 1 0 then repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4lC1 ? r4l until r4l=0 else next if r4 1 0 then repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4C1 ? r4 until r4=0 else next 4 4 8+ 4n * 2 normal advanced 8+ 4n * 2 eepmov notes: 1. the number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. for other cases see section a.3, number of execution states. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for execution of an instruction that transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0. rev. 2.0, 03/02, page 252 of 298 a.2 operation code map table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc beq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) bvs blt bge bsr table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b rev. 2.0, 03/02, page 253 of 298 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a-2 (3) table a-2 (3) table a-2 (3) add mov sub cmp bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl sub adds shll shlr rotxl rotxr not shal shar rotl rotr neg rev. 2.0, 03/02, page 254 of 298 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc rev. 2.0, 03/02, page 255 of 298 a.3 number of execution states the status of execution for each instruction of the h8/300h cpu and the method of calculating the number of states required for instruction execution are shown below. table a.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 rev. 2.0, 03/02, page 256 of 298 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 16.1, register addresses. rev. 2.0, 03/02, page 257 of 298 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 rev. 2.0, 03/02, page 258 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc blt d:8 bgt d:8 ble d:8 bra d:16(bt d:16) brn d:16(bf d:16) bhi d:16 bls d:16 bcc d:16(bhs d:16) bcs d:16(blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1 rev. 2.0, 03/02, page 259 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 bsr d:16 2 2 1 12 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2 rev. 2.0, 03/02, page 260 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 duvxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n+2 * 1 2n+2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1 rev. 2.0, 03/02, page 261 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern jmp @aa:24 jmp @@aa:8 2 2 21 2 2 jsr jsr @ern jsr @aa:24 jsr @@aa:8 2 2 21 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc@ers, ccr ldc@(d:16, ers), ccr ldc@(d:24,ers), ccr ldc@ers+, ccr ldc@aa:16, ccr ldc@aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @-erd mov.b rs, @aa:8 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 rev. 2.0, 03/02, page 262 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16,ers), rd mov.w @(d:24,ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16,erd) mov.w rs, @(d:24,erd) 2 3 2 1 1 2 4 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 2 mov mov.w rs, @-erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16,ers), erd mov.l @(d:24,ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers,@erd mov.l ers, @(d:16,erd) mov.l ers, @(d:24,erd) mov.l ers, @-erd mov.l ers, @aa:16 mov.l ers, @aa:24 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movfpe movfpe @aa:16, rd * 2 21 movtpe movtpe rs,@aa:16 * 2 21 rev. 2.0, 03/02, page 263 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1 rev. 2.0, 03/02, page 264 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16,erd) stc ccr, @(d:24,erd) stc ccr,@-erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1 rev. 2.0, 03/02, page 265 of 298 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n subx subx #xx:8, rd subx. rs, rd 1 1 trapa trapa #xx:2 2 1 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 note: 1. n:specified value in r4l and r4. the source and destination operands are accessed n+1 times respectively. 2. cannot be used in this lsi. rev. 2.0, 03/02, page 266 of 298 a.4 combinations of instructions and addressing modes table a.5 combinations of instructions and addressing modes addressing mode mov pop, push movfpe, movtpe add, cmp sub addx, subx adds, subs inc, dec daa, das mulxu, mulxs, divxu, divxs neg extu, exts and, or, xor not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc andc, orc, xorc nop data transfer instructions arithmetic operations logical operations shift operations bit manipulations branching instructions system control instructions block data transfer instructions bwl bwl wl b b b #xx rn @ern @(d:16.ern) @(d:24.ern) @ern+/@ern @aa:8 @aa:16 @aa:24 @(d:8.pc) @(d:16.pc) @@aa:8 bwl bwl bwl b l bwl b bw bwl wl bwl bwl bwl b b b bwl b w w bwl w w bwl w w bwl w w b b bwl w w bwl w w wl bw functions instructions rev. 2.0, 03/02, page 267 of 298 appendix b i/o port block diagrams b.1 i/o port block 5(6 goes low in a reset, and 6%< goes low in a reset and in standby mode. pdr pucr pmr pcr pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register trgv internal data bus pull-up mos legend figure b.1 port 1 block diagram (p17) rev. 2.0, 03/02, page 268 of 298 pdr pucr pmr pcr pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register internal data bus pull-up mos legend figure b.2 port 1 block diagram (p14) rev. 2.0, 03/02, page 269 of 298 pdr pucr pcr pucr: port pull-up control register pdr: port data register pcr: port control register internal data bus pull-up mos legend figure b.3 port 1 block diagram (p16, p15, p12, p10) rev. 2.0, 03/02, page 270 of 298 pdr pucr pcr pucr: port pull-up control register pdr: port data register pcr: port control register internal data bus pull-up mos legend figure b.4 port 1 block diagram (p11) rev. 2.0, 03/02, page 271 of 298 pdr pmr pcr pmr: port mode register pdr: port data register pcr: port control register internal data bus txd sci3 legend figure b.5 port 2 block diagram (p22) rev. 2.0, 03/02, page 272 of 298 pdr pcr pdr: port data register pcr: port control register re internal data bus rxd sci3 legend figure b.6 port 2 block diagram (p21) rev. 2.0, 03/02, page 273 of 298 pdr pcr pdr: port data register pcr: port control register sckie internal data bus scki sci3 sckoe scko legend figure b.7 port 2 block diagram (p20) rev. 2.0, 03/02, page 274 of 298 pdr pcr pmr pmr: port mode register pdr: port data register pcr: port control register internal data bus legend figure b.8 port 5 block diagram (p57, p56) rev. 2.0, 03/02, page 275 of 298 pdr pucr pmr pcr pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register internal data bus pull-up mos legend figure b.9 port 5 block diagram (p55) rev. 2.0, 03/02, page 276 of 298 pdr pucr pmr pcr pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register internal data bus pull-up mos legend figure b.10 port 5 block diagram (p54 to p50) rev. 2.0, 03/02, page 277 of 298 pdr pcr os3 os2 os1 os0 tmov pdr: port data register pcr: port control register internal data bus timer v legend figure b.11 port 7 block diagram (p76) rev. 2.0, 03/02, page 278 of 298 pdr pcr tmciv pdr: port data register pcr: port control register internal data bus timer v legend figure b.12 port 7 block diagram (p75) rev. 2.0, 03/02, page 279 of 298 pdr pcr tmriv pdr: port data register pcr: port control register internal data bus timer v legend figure b.13 port 7 block diagram (p74) rev. 2.0, 03/02, page 280 of 298 pdr pcr pdr: port data register pcr: port control register internal data bus ftioa ftiob ftioc ftiod timer w output control signals a to d legend figure b.14 port 8 block diagram (p84 to p81) rev. 2.0, 03/02, page 281 of 298 pdr pcr ftci pdr: port data register pcr: port control register internal data bus timer w legend figure b.15 port 8 block diagram (p80) rev. 2.0, 03/02, page 282 of 298 dec v in ch3 to ch0 a/d converter internal data bus figure b.16 port b block diagram (pb3 to pb0) b.2 port states in each operating state port reset active sleep subsleep standby p17 to p14, p12 to p10 high impedance functioning retained retained high impedance * p22 to p20 high impedance functioning retained retained high impedance p57 to p50 high impedance functioning retained retained high impedance * p76 to p74 high impedance functioning retained retained high impedance p84 to p80 high impedance functioning retained retained high impedance pb3 to pb0 high impedance high impedance high impedance retained high impedance note: * high level output when the pull-up mos is in on state. rev. 2.0, 03/02, page 283 of 298 appendix c product code lineup product type product code model marking package (hitachi package code) h8/3672 flash memory version standard product hd64f3672fp hd64f3672fp lqfp-64 (fp-64e) hd64f3672fx hd64f3672fx lqfp-48 (fp-48f) hd64f3672fy hd64f3672fy lqfp-48 (fp-48b) h8/3670 flash memory version standard product hd64f3672fp hd64f3672fp lqfp-64 (fp-64e) hd64f3670fx hd64f3670fx lqfp-48 (fp-48f) hd64f3670fy hd64f3670fy lqfp-48 (fp-48b) rev. 2.0, 03/02, page 284 of 298 appendix d package dimensions the package dimensions that are shows in the hitachi semiconductor packages data book have priority. hitachi code jedec eiaj mass (reference value) fp-64e ? conforms 0.4 g unit: mm *dimension including the plating thickness base material dimension m 12.0 0.2 10 48 33 116 17 32 64 49 *0.22 0.05 0.08 0.5 12.0 0.2 0.10 1.70 max *0.17 0.05 0.5 0.2 0? e 8? 1.0 1.45 0.10 0.10 1.25 0.20 0.04 0.15 0.04 figure d.1 fp-64e package dimensions rev. 2.0, 03/02, page 285 of 298 hitachi code jedec eiaj mass (reference value) fp-48f 0.4 g * dimension including the plating thickness base material dimension 0.10 0 C 8 0.50 0.1 * 0.17 0.05 0.1 0.05 1.65 max 1.0 12.0 0.2 10 * 0.32 0.05 0.13 36 25 112 37 48 24 13 0.65 12.0 0.2 m 0.30 0.04 1.425 1.45 0.15 0.04 unit: mm figure d.2 fp-48f package dimensions rev. 2.0, 03/02, page 286 of 298 hitachi code jedec jeita mass (reference value) fp-48b 0.2 g * dimension including the plating thickness base material dimension 9.0 0.2 7 * 0.22 0.05 0.08 36 25 112 37 48 24 13 0.5 9.0 0.2 0.08 1.0 0? C 8? 0.5 0.1 * 0.17 0.05 1.70 max m 0.75 0.20 0.04 1.40 0.15 0.04 0.10 0.07 as of january, 2002 unit: mm figure d.3 fp-48b package dimensions rev. 2.0, 03/02, page 287 of 298 main revisions and additions in this edition item page revisions (see manual for details) rev. general precautions on handling of product iii added. 2.0 configuration of this manual iv added. 2.0 preface v notes added. restrictions 1 to 5 when using an on-chip emulator (e10t) for h8/3672 program development and debugging 2.0 1.1 features compact package 1 package added. lqfp-48 (fp-48b) 2.0 1.2 internal block diagram figure 1.1 internal block diagram 2 e10t_0 e10t_1 e10t_2 2.0 1.3 pin arrangement figure 1.2 pin arrangement (fp-64e) 3 44 43 42 41 40 p20/sck3 e10t_2 e10t_1 e10t_0 p84/ftiod note: do not connect nc pins ( these pins are not connected to the internal circuitry). 2.0 1.3 pin arrangement figure 1.3 pin arrangement (fp-48f, fp-48b) 4 34 33 32 31 30 p20/sck3 e10t_2 e10t_1 e10t_0 p84/ftiod note: do not connect nc pins ( these pins are not connected to the internal circuitry). 2.0 txd 46 36 output rxd 45 35 input syrial communication interface (sci) sck3 44 34 i/o 1.4 pin functions table 1.1 pin functions 62.0 rev. 2.0, 03/02, page 288 of 298 item page revisions (see manual for details) rev. e10t e10t_0, e10t_1, e10t_2 41, 42, 43 31, 32, 33 interface pin for e10t emulator 1.4 pin functions table 1.1 pin functions 62.0 2.1 address space and memory map figure 2.1 memory map 8 e10t control program area (4 kbytes) (1-kbyte work area for flash memory programming&e10t) (1-kbyte work area for flash memory programming&e10t) e10t control program area (4 kbytes) h'3fff hd64f3672 hd64f3670 h'4000 h'4fff h'f780 h'4000 h'4fff h'f780 h'fb7f 2.0 bit bit name description 4 3 2 acmp2 acmp1 acmp0 address compare condition select 2 to 0 these bits comparison condition between the address set in bar and the internal address bus. 000: compares 16-bit addresses 001: compares upper 12-bit addresses 010: compares upper 8-bit addresses 011: compares upper 4-bit addresses 1xx: reserved (setting prohibited) 4.1.1 address break control register (abrkcr) 56 2.0 4.2 operation 58 description amended. when the abif and abie bits in abrksr are set to 1, the address break function generates an interrupt request to the cpu. the abif bit in abrksr is set to 1 by the combination of the address set in bar, the data set in bdr, and the conditions set in abrkcr. 2.0 4.2 operation figure 4.2 address break interrupt operation example (3) 59 deleted. 2.0 4.3 usage notes 59 added. 2.0 rev. 2.0, 03/02, page 289 of 298 item page revisions (see manual for details) rev. 5.1 system clock generator figure 5.2 block diagram of system clock generator 61 added. osc 2 osc 1 lpm: low-power mode (standby mode, subsleep mode) lpm 2.0 5.2.1 prescaler s 63 description amended. in active mode and sleep mode, the clock input to prescaler s is determined by the division factor designated by ma2 to ma0 in syscr2. 2.0 bit bit name description 6 5 4 sts2 sts1 sts0 standby timer select 2 to 0 these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, to active mode or sleep mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. the relationship between the specified value and the number of wait states is shown in table 6.1. when an external clock is to be used, the minimum value (sts2 = sts1 = sts0 =1) is recommended. 6.1.1 system control register 1 (syscr1) 66 2.0 6.1.4 module standby control register 2 (mstcr2) 69 deleted. 2.0 section 7 rom 75 description amended. eiot ? e10t reprogramming capability the flash memory can be reprogrammed up to 1,000 times. description deleted. power-down mode 2.0 rev. 2.0, 03/02, page 290 of 298 item page revisions (see manual for details) rev. 7.2.4 flash memory enable register (fenr) 79 description amended. bit 7 (flshe) in fenr enables or disables the cpu access to the flash memory control registers, flmcr1, flmcr2, and ebr1. 2.0 7.3 on-board programming modes table 7.1 setting programming modes 79 description amended. eiot_0 ? e10t_0 2.0 7.3.1 boot mode table 7.2 boot mode operation 81 changed. communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host when data h'55 is received. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation ? measures low-level period of receive data h'00. ? calculates bit rate and sets brr in sci3. ? transmits data h'00 to host as adjustment end indication. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase 2.0 7.4.1 program/program- verify 83 description amended. 7. for a dummy write to a verify address, write 1- byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words or in longwords from the address to which a dummy write was performed. 2.0 rev. 2.0, 03/02, page 291 of 298 item page revisions (see manual for details) rev. 7.4.1 program/program- verify figure 7.3 program/program-verify flowchart 84 start note: * the rts instruction must not be used during the following 1. and 2. periods. 1. a period between 128-byte data programming to flash memory and the p bit clearing 2. a period between dummy writing of h'ff to a verify address and verify data reading set swe bit in flmcr1 write pulse application subroutine wait 1 m s apply write pulse * end sub set psu bit in flmcr1 wdt enable disable wdt wait 50 m s set p bit in flmcr1 wait (wait time=programming time) clear p bit in flmcr1 wait 5 m s clear psu bit in flmcr1 wait 5 m s n= 1 m= 0 wait 4 m s wait 2 m s apply write pulse set pv bit in flmcr1 set block start address as verify address h'ff dummy write to verify address read verify data n ? n + 1 write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area * 2.0 7.4.3 interrupt handling when programming/erasing flash memory figure 7.4 erase/erase- verify flowchart 87 read verify data set block start address as verify address h'ff dummy write to verify address wait 20 m s wait 2 m s ev bit ? 1 note: * the rts instruction must not be used during a period between dummy writing of h'ff to a verify address and verify data reading. n ? n + 1 * 2.0 bit bi name initial r/w description 7 6 5 ? ? ? ? ? ? ? ? ? reserved 9.5.1 port control register 8 (pcr8) 106 2.0 10.3.2 time constant registers a and b (tcora, tcorb) 113 initial value added. tcora and tcorb are initialized to h'ff. 2.0 rev. 2.0, 03/02, page 292 of 298 item page revisions (see manual for details) rev. bit bit name description 2trge tcntv starts counting up by the input of the edge which is selected by tveg1 and tveg0. 0: disables starting counting-up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1: enables starting counting-up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 10.3.5 timer control register v1 (tcrv1) 117 2.0 description amended tcrw selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. bit bit name initial value r/w description 3 tod 0 r/w timer output level setting d 0: output value is 0 * 1: output value is 1 * 2 toc 0 r/w timer output level setting c 0: output value is 0 * 1: output value is 1 * 1 tob 0 r/w timer output level setting b 0: output value is 0 * 1: output value is 1 * 0 toa 0 r/w timer output level setting a 0: output value is 0 * 1: output value is 1 * 11.3.2 timer control register w (tcrw) 130 note: * the change of the setting is immediately reflected in the output value. 2.0 rev. 2.0, 03/02, page 293 of 298 item page revisions (see manual for details) rev. 11.4.1 normal operation figure 11.6 toggle output example (toa = 0, tob = 1) 137 tcnt value h'ffff h'0000 gra grb 2.0 12.1 features 151 description amended. selectable from nine counter input clocks. eight clock sources ( f /64, f /128, f /256, f /512, f /1024, f /2048, f /4096, and f /8192) or the internal oscillator can be selected as the timer-counter clock. when the internal oscillator is selected, it can operate as the watchdog timer in any operating mode. 2.0 12.2.1 timer control/status register wd (tcsrwd) 152 tcsrwd performs the tcsrwd and tcwd write control. tcsrwd also controls the watchdog timer operation and indicates the operating state. tcsrwd must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. 2.0 bit r/w 7 r/w 5 r/w 3 r/w 1 r/w 13.3.4 transmit data register (tdr) 158 initial value added. tdr is initialized to h'ff. 2.0 bit bit name initial value r/w 2 tend 1r 13.3.7 serial status register (ssr) 163 2.0 15.1 when using internal power supply step-down circuit 207 description amended. connect the external power supply to the v cc pin, and connect a capacitance of approximately 0.1 f between v cl and v ss , as shown in figure 15.1. 2.0 15.2 when not using internal power supply step-down circuit 208 description amended. when the internal power supply step-down circuit is not used, connect the external power supply to the v cl pin and v cc pin, as shown in figure 15.2. 2.0 rev. 2.0, 03/02, page 294 of 298 item page revisions (see manual for details) rev. values item symbol test condition min typ max unit reprogramming count n wec ??? 1000 times 17.2.6 flash memory characteristics (preliminary) table 17.7 flash memory characteristics (preliminary) 231 2.0 b.1 i/o port block figure b.10 port 5 block diagram (p54 to p50) 267 pdr pucr internal data bus pmr pcr 2.0 rev. 2.0, 03/02, page 295 of 298 index a/d converter....................................... 195 a/d conversion time.......................... 202 external trigger input ......................... 203 sample-and-hold circuit ..................... 202 scan mode ........................................ 201 single mode ...................................... 201 absolute maximum ratings .................. 219 address break.........................................55 addressing modes...................................27 absolute address.................................28 immediate ...........................................28 memory indirect..................................29 program-counter relative....................29 register direct ....................................27 register indirect ..................................27 register indirect with displacement.....28 register indirect with post-increment .. 28 register indirect with pre-decrement... 28 clock pulse generators............................61 condition field .......................................26 condition-code register (ccr) ..............11 cpu..........................................................7 effective address ....................................29 effective address extension ....................26 electrical characteristics ....................... 219 ac characteristics............................. 226 dc characteristics............................. 221 exception handling.................................41 nmi ....................................................48 reset exception handling....................48 stack status.........................................50 trap instruction ...................................41 flash memory...........................................75 boot mode ..........................................80 boot program.......................................79 erase/erase-verify...............................85 erasing units ........................................75 error protection ...................................88 hardware protection ............................88 program/program-verify......................83 programming units...............................75 programming/erasing in user program mode ...............................................82 software protection .............................88 general registers ....................................10 i/o ports..................................................91 i/o port block diagrams....................267 instruction set .........................................16 arithmetic operations instructions. 18, 19 bit manipulation instructions......... 21, 22 block data transfer instructions..........25 branch instructions..............................23 data transfer instructions....................17 logic operations instructions ..............20 shift instructions .................................20 system control instructions .................24 internal power supply step-down circuit ..........................................................207 interrupt internal interrupts ................................49 interrupt response time ......................51 irq3 to irq0 interrupts ......................48 nmi interrupt ......................................48 wkp5 to wkp0 interrupts...................48 large current ports......................................1 memory map.............................................8 module standby function ........................73 on-board programming modes ...............79 operation field........................................26 package.....................................................1 package dimensions..............................284 rev. 2.0, 03/02, page 296 of 298 pin arrangement ....................................... 3 power-down modes................................. 65 sleep mode ......................................... 72 standby mode ..................................... 72 subsleep mode.................................... 72 prescaler s .............................................. 63 product code lineup............................. 283 program counter (pc)............................. 11 pwm operation .................................... 140 register abrkcr..................... 56, 211, 214, 217 abrksr ..................... 57, 211, 214, 217 adcr........................ 200, 211, 214, 217 adcsr...................... 199, 211, 214, 217 addra ..................... 198, 211, 214, 217 addrb ..................... 198, 211, 214, 217 addrc ..................... 198, 211, 214, 217 addrd ..................... 198, 211, 214, 217 barh.......................... 57, 211, 214, 217 barl .......................... 57, 211, 214, 217 bdrh.......................... 57, 211, 214, 217 bdrl .......................... 57, 211, 214, 217 brr........................... 164, 210, 213, 216 ebr1 ........................... 78, 210, 213, 216 fenr........................... 79, 210, 213, 216 flmcr1...................... 77, 210, 213, 216 flmcr2...................... 78, 210, 213, 216 gra .......................... 135, 210, 213, 216 grb........................... 135, 210, 213, 216 grc........................... 135, 210, 213, 216 grd .......................... 135, 210, 213, 216 iegr1.......................... 43, 212, 215, 218 iegr2.......................... 44, 212, 215, 218 ienr1.......................... 45, 212, 215, 218 irr1 ............................ 46, 212, 215, 218 iwpr........................... 47, 212, 215, 218 mstcr1...................... 69, 212, 215, 218 pcr1 ........................... 93, 212, 215, 217 pcr2 ........................... 96, 212, 215, 217 pcr5 ......................... 100, 212, 215, 217 pcr7 ......................... 104, 212, 215, 217 pcr8 ......................... 106, 212, 215, 217 pdr1 ........................... 93, 211, 214, 217 pdr2 ........................... 97, 211, 214, 217 pdr5 ......................... 100, 211, 214, 217 pdr7 ......................... 104, 211, 214, 217 pdr8 ......................... 107, 211, 214, 217 pdrb......................... 110, 212, 215, 217 pmr1........................... 92, 212, 215, 217 pmr5........................... 99, 212, 215, 217 pucr1......................... 94, 211, 214, 217 pucr5....................... 101, 211, 214, 217 rdr........................... 158, 211, 214, 216 rsr .................................................. 158 scr3.......................... 160, 210, 213, 216 smr........................... 159, 210, 213, 216 ssr............................ 162, 211, 214, 216 syscr1 ....................... 66, 212, 215, 218 syscr2 ....................... 68, 212, 215, 218 tcnt......................... 135, 210, 213, 216 tcntv...................... 113, 210, 213, 216 tcora...................... 113, 210, 213, 216 tcorb...................... 113, 210, 213, 216 tcrv0....................... 114, 210, 213, 216 tcrv1....................... 117, 210, 213, 216 tcrw........................ 129, 210, 213, 216 tcsrv ...................... 116, 210, 213, 216 tcsrwd................... 152, 211, 214, 217 tcwd ....................... 153, 211, 214, 217 tdr........................... 158, 211, 213, 216 tierw....................... 131, 210, 213, 216 tior0........................ 133, 210, 213, 216 tior1........................ 134, 210, 213, 216 tmrw....................... 129, 210, 213, 216 tmwd....................... 153, 211, 214, 217 tsr................................................... 158 tsrw ........................ 131, 210, 213, 216 register field..........................................26 serial communication interface 3(sci3) 155 asynchronous mode.......................... 169 bit rate............................................... 164 break detection................................. 192 clocked synchronous mode .............. 177 framing error ..................................... 173 rev. 2.0, 03/02, page 297 of 298 mark state......................................... 192 multiprocessor communication function ...................................................... 184 overrun error ..................................... 173 parity error ........................................ 173 stack pointer (sp) ...................................11 system clock generator ..........................61 timer v.................................................111 timer w................................................125 vector address........................................42 watchdog timer....................................151 rev. 2.0, 03/02, page 298 of 298 h8/3672 series hardware manual publication date: 1st edition, march 2001 2nd edition, march 2002 published by: business planning division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 2001. all rights reserved. printed in japan. |
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